坐井观天啊，
上次去转悠比美的还当回事，
周日商场超市全关门，
就火车站附近有个别营业，



【 在 capablanca 的大作中提到: 】
: 老欧洲大部分人早不信教了。
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FROM 175.171.29.*

去it 版扫两天盲你也不至于这么无知了


【 在 RaorOfPanda 的大作中提到: 】
:
: 明摆着有个谁也管不了的大强盗大流氓在那个片区收天价保护费
: 脑袋被驴踢了还是被门挤了才会去那个片区摆摊开店？！
: ...................
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FROM 175.171.29.*

【 以下文字转载自 METech 讨论区 】
发信人: cbzcbz999 (xdfae), 信区: METech
标  题: 坂本幸雄：中国大陆半导体水平落后台湾一大截
发信站: 水木社区 (Tue May 31 17:27:52 2022), 站内
  
宣告破产的紫光集团前高级副总裁、前日本尔必达社长坂本幸雄接受访问时说，中国大陆半导体产业的实力不管在研发、生产和产品良率方面落后台湾、韩国和美国一大截。
  
据日经新闻报道，坂本指出，中国大陆占世界半导体生产的比重为15%，但其中英特尔等外资企业占60%，中企的比重仅40%，大陆半导体产业当前的要务是研发，但肩负半导体产业发展者主要是出自台湾，多为成品良率改善等工序管理方面的人才，在从零开始创造价值的研发方面缺乏经验。
  
坂本说，大陆半导体实力与世界顶尖水平的差距很大，在DRAM领域处于中国顶尖水平的长鑫存储，与三星电子相比落后4代左右；而在NAND快闪记忆体领域，大陆据称顶尖的长江存储在去年8月启动128层3D NAND的量产，虽已启动192层的试产，但生产的数量过少，达不到讨论竞争力的水平。
  
坂本介绍，在运算用逻辑晶片领域，即使是顶尖的中芯国际，最好的产品也只是14奈米，这已是七、八年前的技术，而台积电正在开发2纳米的产品，中芯国际以工序管理的工程师为中心，或许难以推进新技术的开发，加上美国的制裁，更难以引进尖端的半导体生产设备，无法跨入价值巨大的处理器领域，经营资源完全被用在增加14奈米以上的产能，如果缺乏在三、四年后追上台积电的雄心，差距会不断扩大。
  
另据BusinessKorea报导，韩国进出口银行旗下海外经济研究院（OERI）预估，中国大陆在DRAM和NAND快闪记忆体方面与韩国的技术落差分别达五年和两年。
  
大陆半导体业的产品良率也很低。 OERI分析指出，长鑫存储2019年开始量产第一代10奈米DRAM，但两年多过去，良率仍只有75%；第二代DRAM的良率更只有40%。
【 在 RaorOfPanda 的大作中提到: 】
:
: 对，就你可明白了
: 你明白的那些玩意几乎没有一个不是造谣！
: ...................
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FROM 42.84.230.*

是你文科生，
拿数字说话都不懂，
60percent,
知道什么概念吗？
广州黑人也多，
然后你就会说广州现在不是社会主义了吗？

【 在 capablanca 的大作中提到: 】
: 法国离婚率高单身母亲多，黑人移民多，这成了tg洗脑了，你家tg才这么洗，你是跪久了不敢直视了吧。
--
FROM 192.102.205.*

网上一堆techinsight 报告，
搜搜就知道了，
专门有人拆解分析，
具体不給你扯了， 你就自嗨可以了，
嗨完去窝里睡觉了，
这个和一般老百姓关系不大，
而且tg 給韩企那么多优惠条件开厂
也是韩企这么强势的原因， 所以羊毛出在羊身上


Abstract and Figures

In this paper, we will present comparison of DRAM cell patterning between ArF immersion and EUV lithography which will be the main stream of DRAM lithography. Assuming that the limit of ArF immersion single patterning is around 40nm half pitch, EUV technology is positioned on essential stage because development stage of device manufacturer is going down sub-40nm technology node. Currently lithography technology, in order to improve the limitation of ArF immersion lithography, double patterning technology (DPT) and spacer patterning technology (SPT) have been examined intensively. However, double patterning and spacer patterning technology are not cost-effective process because of complexity of lithography process such as many hard mask stacks and iterative litho, etch process. Therefore, lithography community is looking forward to improving maturity of EUVL technology. In order to overcome several issues on EUV technology, many studies are needed for device application. EUV technology is different characteristics with conventional optical lithography which are non-telecentricity and mask topography effect on printing performance. The printed feature of EUV is shifted and biased on the wafer because of oblique illumination of the mask. Consequently, target CD and pattern position are changed in accordance with pattern direction, pattern type and slit position of target pattern.1 For this study, we make sub-40nm DRAM mask for ArF immersion and EUV lithography. ArF attenuated PSM (Phase Shift Mask) and EUV mask (LTEM) are used for this experiment; those are made and developed by in-house captive maskshop. Simulation and experiment with 1.35NA ArF immersion scanner and 0.25NA EUV full field scanner are performed to characterize EUV lithography and to compare process margin of each DRAM cell. Two types of DRAM cell patterns are studied; one is an isolation pattern with a brick wall shape and another is a storage node pattern with contact hole shape. Line and space pattern is also studied through 24nm to 50nm half pitch for this experiment. Lithography simulation is done by in-house tool based on diffused aerial image model. EM-SUITE and Solid-EUV are also used in order to study characteristics of EUV patterning through rigorous EMF simulation. We also investigated shadowing effect according to pattern shape and design rule respectively. We find that vertical to horizontal bias is around 2nm on 32nm to 40nm half pitch line and space pattern. In the case of DRAM cell, we also find same result with line and space pattern. In view of mask-making consideration, we optimize absorber etch process. So we acquire vertical absorber profile and mask MTT(Mean To Target) within 10% of target CD through several pitch. Process windows and mask error enhancement factors are measured with respect to several DRAM cell pattern. In the case of one dimensional line and space and two dimensional brick wall pattern, vertical pattern shows the best performance through various pitches because of lower shadowing effect than horizontal pattern. But in case of contact hole DRAM cell pattern such as storage node pattern, it has bigger MEF value than one or two dimensional pattern because of independency of shadowing effect. Finally, we compare with 2x, 3x and 4x DRAM cell patterning performance in terms of pattern fidelity, slit CD uniformity and shadowing effect.

Resolution limit with various lithography technology


SUMMARY & DISCUSSION
EUV mask was manufactured with good pattern fidelity and absorber profile and subsequently exposed in EUV ADT at
IMEC. In view of resolution, EUV ADT shows 28nm resolution. It’s not clearly dissolved but possibility can be assessed
for 24nm. Though mask layouts were not corrected for shadowing effect, but good CD uniformity values are achieved
also for each pattern directions. Correction of offset between each patterns seem to give acceptable CD uniformity results
for 32nm L/S. In addition, influence of mask shadowing effect was studied for various pattern shapes and directions.
Brick wall pattern is most sensitive to shadowing effect while contact hole pattern is not much affected by it. Finally,
EUV and ArF immersion technologies are compared in view of DRAM cell patterning. EUV shows promising results
even down to D2x node which double patterning is necessary for ArF immersion.
…



【 在 RaorOfPanda 的大作中提到: 】
:
: 合肥长鑫主打20nm、17nm
: 这俩制程的dram要euv干什么用？
: ...................
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修改:ibm221 FROM 175.171.29.*
FROM 175.171.29.*