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FROM 192.102.204.*

@polejoe
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FROM 192.102.204.*

继续 JD
Software quality engineer


Job Description
This position is for:
Permanent blue badge employees only.
Job Details:
Job Description:
Deep understanding of Quality standards like GS5000, ISO 9000 and models like CMMI. Authors detailed software quality requirements to meet Intel quality standards. Works with product development teams throughout the product development life cycle to ensure software quality requirements and goals are established and met. Trains the team on quality engineering practices. Drives effective software practices to ensure project work products comply with applicable standards, requirements. Provides input into program deliverables /milestones regarding quality (resources, schedule, goals, etc.) Drives actions from previous postproject reviews to closure as part of Product development team (PDT), including process/work product audits.
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum qualifications and are considered a plus factor in identifying top candidates:

Minimum Qualifications: You should possess a bachelors or master's degree in Computer Science, Information Systems, Operations Management, or a related discipline. You must also have a minimum of at least 5 years of experience. Candidates must have experience in the following: Improving the quality of software, data analysis and metrics creation techniques, knowledge of software development life cycle, legal & security processes and programming/scripting languages.
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FROM 192.102.204.*

泥煤的水木的验证码也太难看了吧，换好几次才能全认对，这是防机器人还是猜谜呢？
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修改:polejoe FROM 192.102.204.*
FROM 192.102.204.*

Modem SoC Design/VerificationActions

Job Description:
Full-time position at Intel in a leading research and development organization as an experienced modem SoC designers, with emphasis on the following critical skills:
?Hands-on experience in ASIC design flow and verification of digital design.
?Experience in integrating modem subsystem IP with other IPs or hard macro (CPU, bus/NoC, I/O, DDR, trace and debug, etc.) with optimized power/area, as well as in defining/verifying PLL / clocking.
?Experience in clock gating and power management strategy.
?Understand and communicate with back-end team to understand floor planning and timing closure issues and communicate with RTL design teams to help address.

The successful candidate will work closely with a team of hardware and firmware designers specializing in modem subsystem, and a team of SoC level IP integration and pre/post-silicon verification engineers to build world-class commercial quality SoC.

Qualifications:
- PhD or master's degree in Electrical Engineering, especially on computer architecture and digital design.
- Proven track record of taping out large SoC systems containing embedded processors.
- Have 5+ years of experience in ASIC design flow and verification of digital design.
- Strong communication skills to interface with various teams throughout the company.
- Familiar with UPF flow for power and voltage domain simulation
- In-depth knowledge of low-power, high-speed, and low-area design concepts.
- Experience with linting/CDC/formal equivalence/synthesis/netlist generation tools.
- Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology.
- Verification experience of PCIe, bus fabric, NOC, AHB, AXI bus architecture in UVM environment.
- Knowledge of Verilog/System Verilog, digital simulation and debug.
- Familiarity with communication theories and 4G/5G modem algorithm is highly desirable.
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FROM 192.102.204.*