大家好，新年快乐~~~
新年招聘贴，中科睿芯现有如下岗位，有兴趣的IC小伙伴加入我们吧，欢迎投递简历，邮箱为sunxiaochen@smart-core.cn，薪酬福利待遇有竞争力哦。有任何问题可以加微信13501350019沟通哦。
SoC / ASIC Design
Responsibilities:
- Involved in all phases of product development, from proving-out initial high-level concepts down to tape out
- Design and implement microarchitecture
- Work with software and verification team
Requirement:
- Major in CS, EE or related, BSEE required
- 5+ years' of experience in SOC design related field
- Industry experience in SD/eMMC design or PCIE design
- Experience with BUS protocols for IO-device integration
- Experience with I/O protocols
- Familiar with Verilog/VHDL, and ASIC design flow
SoC Verification
Responsibilities:
- Involved in all phases of product development, from programming DV test-plan, building test-bench, writing test-cases, running regression to debugging fail cases
- Responsible for using Verilog and System-Verilog to develop the top-level verification environment
Requirement:
-Major in CS, EE or related, BSEE required
- Good understanding of SoC verification methodology such as UVM methodology
- Implement test-bench and test-case according to test-plan
- Familiar in the use of verification tools
- Experience with architecture is preferred
Design Implementation
Responsibilities:
- Responsible for digital logic synthesis, STA, formal verification and low power check
- Develop timing constraint and low power design constraint
- Co-work with physical design team for timing closure
- Responsible to optimize digital frontend flow qualification
Requirement:
- Major in CS, EE or related, BSEE required
- 2~10 years of hands-on experience in design implementation related field
- Strong knowledge of digital logic design, synthesis, STA, formal verification, etc.
- Familiar with common UNIX utility such as Shell, Perl, TCL[/face]
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