岗位描述：
1. 参与深度学习项目整体解决方案设计、需求分析、测试工作;
2. 参与核心算法的开发, 并且对算法结果进行测试、验证；
3. 跟踪和学习最前言的深度学习算法, 为深度学习的应用提供支撑;
4. 能够通过技术手段, 提高产品交付质量;
岗位要求：
1、计算机相关专业，硕士及以上学历;
2、逻辑思维清晰，积极主动，责任心和抗压能力强，具备良好的沟通表达能力;
3、了解机器学习/深度学习/图像处理相关算法, 并且对视觉计算和深度学习有浓厚兴趣;
4、掌握C/C++/python编程语言, 并且有良好的编程风格和工作习惯；
5、每周可以4天以上, 连续实习半年以上, 2025年毕业生,优先参与春招; 2026年毕业生,优先参与秋招...
薪资: 200~400, 具体可谈...
联系方式: 站内或 licaijun@cambricon.com
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修改:muerte FROM 101.254.121.*
FROM 101.254.121.*
Job Summary
As a member of the core backend team, you will be responsible for the physical implementation (from netlist to tapeout) of a highly complex SOC utilizing state of the art process technology.
Description
o Work with FE team to understand chip architecture and drive physical aspects early in design cycle.
o Design automation; Construct, Guide, Modify, Enhance Timing tools and flows.
o Top level floorplan, partition floorpan, P&R, timing and physical sign off.
Key Qualification
o The ideal candidate will have a minimum of 3 years of physical design experience, with recent successful tapeouts in deep sub-micron technology.
o Expert in top /block level P&R implementation, including floorplanning, clock & power distribution, timing closure, physical & electrical verification.
o Experienced in industry standard tools, understand their capabilities and underlying algorithms.
o Strong communication skills.
o Familiar with sub-micro Synthesis, PR and power sign off tool is a plus.
o Experience with DDR, PCIE is a plus.
o Strong scripting abilities in Python are needed; TCL or Makefile is a plus.
o Experience in methodology of Technology under 16nm is a plus.
o Experience in large - scale chip design is a plus.
Education
BS/MS CE or EE.
【 在 jiu 的大作中提到: 】
: 有硬件工程师的职位吗？
:
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FROM 101.254.121.*