阿里达摩院平头哥正在招数字前端验证工程师，要求要有三年以上的验证经验，待遇丰厚，有意者请发邮件至me_basic@163.com或者站内信私聊。
职位描述
* Work with Architecture and Software teams to ensure micro-architecture and design is fully verified/validated across multiple platforms
* Define testplan for specific block level design and execute the tesplan to achieve function verfication closure
* Development of reusable block level UVM verification enviroment with checker/monitor/driver etc,
职位要求
* Masters degree desired, Bachelor's degree in CS/EE is required. 3+ years of relevant experience in ASIC verification field.
* Should have the test plan definition and execution experience
* Fluent in System Verilog and scripting languages such as Python or Perl.
* Must have intimate knowledge of UVM methodology.
* Experience in the verification of SoC and IO IPs such as PCIE, DDR, and peripherals such as UART/SPI/I2C/GPIO/TIMER/WATCHDOG etc.
* Knowledgeable about assertions and functional coverage
* Experience with code coverage, formal verification tools; familiarity with evolving verification methodologies.
* Experience with ARM based C/Assemblly test is a big plus
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