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芯片验证专家(CPU)
岗位描述
1. 参与验证面向各种应用领域的32/64位嵌入式CPU;
2. 参与构建处理器验证流程及验证环境;
3. 参与研发验证工具、环境及方法学相关前沿领域技术
岗位要求
1. 精通以function coverage为驱动的验证流程;
2. 精通UVM验证方法学,对受限随机测试有深刻理解;
3. 熟悉数字电路设计流程;
4. 熟悉处理器体系结构,包括CPU编程模型、流水线架构;
5. 有以下工作经历尤佳:
1)参与过具体CPU验证;
2)参与过处理器reference model开发;
3)精通汇编语言书写;
4)精通verilog/system verilog;
5)精通perl/tcl等脚本语言;
6)精通C/C++等编程语言
芯片验证专家
岗位描述:
* Work with Architecture and Software teams to ensure micro-architecture and design is fully verified/validated across multiple platforms
* Contribute significantly to verification infrastructure development
* Development of System Verilog/UVM based protocol/traffic generators/checkers, development of test plan based on functional requirements
岗位要求:
Masters degree desired, Bachelor's degree in CS/EE is required. 5+ years of relevant experience in ASIC verification field.
* Should have worked on developing/implementing test plans at the chip-level for complex ASICs.
* Fluent in System Verilog and scripting languages such as Python or Perl.
* Must have intimate knowledge of UVM methodology.
* Experience in the verification of SoC and other IPs such as CPU Subsystem, Ethernet, PCIE, DDR, Serdes etc.
* Knowledgeable about assertions and functional coverage
* Experience with code coverage, formal verification tools; familiarity with evolving verification methodologies.
* Very good communication skills and ability and desire to work in a geographically diverse team environment.
* Will be responsible for definition, development and execution of self-checking tests for complex digital ASICs
P.S. Please submit the English version of resume
芯片验证专家(IO)
岗位描述:
* Work with Architecture and Software teams to ensure micro-architecture and design is fully verified/validated across multiple platforms
* Define testplan for specific block level design and execute the tesplan to achieve function verfication closure
* Development of reusable block level UVM verification enviroment with checker/monitor/driver etc,
岗位要求:
* Masters degree desired, Bachelor's degree in CS/EE is required. 3+ years of relevant experience in ASIC verification field.
* Should have the test plan definition and execution experience
* Fluent in System Verilog and scripting languages such as Python or Perl.
* Must have intimate knowledge of UVM methodology.
* Experience in the verification of SoC and IO IPs such as PCIE, DDR, and peripherals such as UART/SPI/I2C/GPIO/TIMER/WATCHDOG etc.
* Knowledgeable about assertions and functional coverage
* Experience with code coverage, formal verification tools; familiarity with evolving verification methodologies.
* Experience with ARM based C/Assemblly test is a big plus
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