【 以下文字转载自 METech 讨论区 】
发信人: saga0530 (水桶*民主精蝇都去死！！！), 信区: METech
标  题: IBM芯片设计中心封装与信号完整性组招聘实习生
发信站: 水木社区 (Tue Aug 21 11:30:30 2012), 站内

代发帖，勿回站内

IBM芯片设计中心封装与信号完整性组招聘实习生

IBM上海/北京招聘实习生
China Design Center Packaging/Noise Group
Job Requirements:
1. Solid knowledge and industry experience in following areas:
- Package/system design experience
- Familiar with signal integrity/power integrity (SI/PI) analysis basis (modeling, simulation, tools, etc)
- Familiar with chip-package-board co-design concept and management
- Good ASIC backend design knowledge is a plus.
2. Good grasp of Perl/TCL scripts under Linux/Unix environment.
3. EE/ME/CS related background in system/chip design
4. Good communication skill in both English and Mandarin
5. Strong teamwork sense and self-motivation is required.
6. Strong technical leadership will be important consideration for senior positions

Job Scopes & Responsibilities:
IBM ASIC Packaging/Noise design engineer is responsible for large scale ASIC package design&analysis, system-module SI/PI co-simulation and ASIC on die power bus design based on IBM 65nm, 45nm, 32nm and beyond technology as well as 3DIC/TSV with IBM/industry leading EDA tools. The work scope includes one or more of following areas:
- Supporting IBM sales team and customer on IBM early package consulting and evaluation
- Working with customer to define package netlist based on image/package co-design methodology
- Package ERC/SI/PI checking and package layout optimization
- Support customer on system-module SI/PI co-simulation
- Refine Pkg/Noise design methodology in China Design Center
- Image/Power Bus design and optimization
- Cooperate with chip physical designer on IO planning and noise awareness block optimization
- Power bus noise analysis(compression, variation, min voltage etc) using IBM tool
- Chip/package decoupling solution optimization          

Please send your Chinese and English resume in ONE word/pdf file to
yinweny@cn.ibm.com
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