【NVIDIA社招】后端工程师以及验证工程师请到碗里来
一．公司简介
NVIDIA (英伟达™)(www.nvidia.cn)公司(纳斯达克代码：NVDA)是全球视觉计
算技术的行业领袖及GPU(图形处理器)的发明者。作为高性能处理器的GPU可在工作站、
个人计算机、游戏机和移动设备上生成令人叹为观止的互动图形效果。公司在全球拥有
超过8000名员工，总部在加利福尼亚州圣克拉拉。
工作地址：上海研发中心【上海申江路5709号（秋月路26号）矽岸国际2号楼】
二．投递方式
简历发送至HR(Yvette SHEN)邮箱:yvettes@nvidia.com；
三．职位详情
ASIC Physical Design engineer
As a senior member of our ASIC-PD team, you'll be working on streamlining
the chip infrastructure process across product designs, focusing on full
chip layout planning (partitioning, planning clock distribution and other
structure, methodology), partition/full chip timing closure (primetime
scripts, other tools, etc) and gate-level design of high-speed logic
RESPONSIBILITIES:
• Chip integration and netlist generation
• -Synthesis, Formal verification, netlist quality check
• Work in conjunction with Place and Route Engineers to achieve timing
closure for both partition level and full chip level
• Develop and enhance entire timing flow from frontend (pre-layout) to
backend (post-layout) at both chip and block level.
• Develop custom timing scripts using tcl/primetime for clock skew
analysis, special circuits such as clock dividers, core logic <-> IO macros
interfaces such as PCI-E, Frame-Buffer/Memory, TMDS, etc.
• Develop flow to physically partition and floorplan the entire chip.
• Develop scripts for performing ECO's.
MINIMUM REQUIREMENTS:
• BS or MS in Electrical Engineering or Computer Science
• Above 3 years of relevant ASIC experience ideally with a focus in
the chip integration /synthesis/formal and timing closure
• - Excellent scripts skills
• - Excellent written and verbal communication skills in English
• - Ability to multiplex many issues, set priorities, and work in a
team environment
• - Keep up to date with leading edge technologies
ASIC Verification Engineer
Job Description/Qualifications:
RESPONSIBILITIES:
• RTL verification for various control logic and clocking logic in
GPU/tegra chips.
• Develop and maintain verification environment at both full chip &
unit level
• Code/functional coverage analysis
• Responsible for running both RTL & gate level simulation
• Develop testing and regression methodologies
• Develop/maintain/enhance environment tools/scripts/makefiles
MINIMUM REQUIREMENTS:
• BSEE/MSEE/BSCS/MSCS with 3+/5+ years of experience in ASIC
verification
• Proficient in Verilog HDL
• Familiar with logic simulators and debug tools (VCS, NCSIM, Verdi
and etc.)
• Working knowledge in C/C++, Makefile
• Must have strong programming skills in one or more scripting
languages: TCL, Perl, Python
• Knowledge/experience in one of the below areas is a big plus
• + UVM/VMM experience
• + ARM based SoC verification experience PCIE/USB verification
experience
• + CPU verification experience Clocking verification experience
 
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FROM 203.18.50.*