IC backend design and silicon validation internship in NXP Shanghai & Suzhou
NXP Semiconductors N.V. (NASDAQ: NXPI) enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the secure connected vehicle, end-to-end security & privacy and smart connected solutions markets. Built on more than 60 years of combined experience and expertise, the company has 45,000 employees in more than 35 countries.

Currently we are seeking several IC backend design and silicon validation interns in NXP Shanghai and Suzhou which are open to master students to graduate no earlier than 2017 with detailed job description as below. Interested candidates please send you updated resume incl. technical strength and project experiences to hui.qian@nxp.com.
1. Silicon Validation Intern
Location: Suzhou
Responsibilities:
-    Apply skills and knowledge in both hardware and software to perform Pre or Post Silicon validation tasks for Freescale microcontroller products
-    To define the validation plan, and create or execute validation test
-    Design and layout the validation board to bring up new system for fresh IC
-    Work with other cross functional teams in China and oversea to specify, verify and improve SoC quality and timeliness to production

Requirements:
-    Master or Bachelor Degree, electronic or microelectronic
-    Working knowledge in C/C++, Makefile
-    Big plus with experience in ARM M0, M0+ and M4 based MCU
-    Big plus with experience in IAR and CodeWarrior debugger Tool
-    With the FPGA development experience is plus
-    Fluent in writing and speaking English
-    Can work efficiently either in a team or an independent environment

2. IC Backend Design Engineer Intern
Location: Shanghai
Responsibilities:

-    Work with the global design team to do complex SOC physical implementation for deep submicro design.
-    Participates in chip level and block level backend design for complex SOC designs.
-    Responsible for RTL to GDS flow including CPF definition, logic/physical synthesis, die size estimation, floor-planning, power planning, CTS, place and route, STA, signal integrity, timing closure, formal verification, DFM, DRC/LVS etc.

Requirements:
-    University degree in microelectronics engineering or equivalent, master degree or above is preferred;
-    Relevant Experience in floor-planning, power planning, place and route, STA, IR drop and signal integrity, DRC/LVS;
-    Good understanding on soc backend flow and process, special for partition flow;
-    Good communication skills is must, English language proficiency.
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