【NVIDIA社招】英伟达上海热招ASIC Timing Engineer (Clock)

一．公司简介
        NVIDIA (英伟达™)(www.nvidia.cn)公司(纳斯达克代码：NVDA)是全球视觉计
算技术的行业领袖及GPU(图形处理器)的发明者。作为高性能处理器的GPU可在工作站、
个人计算机、游戏机和移动设备上生成令人叹为观止的互动图形效果。公司在全球拥有
超过8000名员工，总部在加利福尼亚州圣克拉拉。
工作地址：上海研发中心【上海申江路5709号（秋月路26号）矽岸国际2号楼】

二．投递方式
感兴趣请的请将简历发送至：yvettes@nvidia.com；邮件注明“BBS”
我们会认真对待每份简历，保证每份简历都有是否通过简历筛选的回复。同时欢迎随时
电话或邮件咨询职位详情，申请进度等等：021-61043660

三．职位详情
1. ASIC Timing Engineer (Clock)
    The NVIDIA Clocks group is looking for an ASIC engineer with
extensive experience in high-speed logic design and timing. The complexity
of clocking structure has grown substantially in order to support high
frequency clock domains. Modern clocking design needs to balance high
frequency clocks with power, DFT, noise, circuit and physical design
constraints.

Responsibilities:
- Perform Synthesis & STA on the designed high speed clock logics.
- Constraint setup and validation in standard & in-house tool flow
- Work in conjunction with Place and Route Engineers to achieve timing
closure
- Develop custom timing scripts using tcl/primetime for clock skew analysis,
special circuits such as clock dividers/switchs, OCC & IO macros interfaces
- Develop scripts for performing ECO's.
- Develop and enhance entire timing flow from frontend (pre-layout) to
backend (post-layout) at both chip and block level.

MINIMUM REQUIREMENTS:

-BS / MS in electrical / computer engineering and related.
-Above 2 years of relevant ASIC experience ideally with a focus in the chip
timing/synthesis/formal closure
-Excellent TCL/Perl scripts skills
-Excellent analytical and problem solving skills
-Fluent English (both written and spoken) and excellent communication skills
-Ability to multiplex many issues, set priorities, and work in a team
environment
-Keep up to date with leading edge technologies
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FROM 203.18.50.*