Responsibilities:
Module level RTL coding;
Module level Documentation;
Backend script mainennance and bit/load file generation;
Document / source code maintenance;
Simulation regression test running;
Simulation environment script maintenance;
Requirements:
Good at Verilog/VHDL RTL coding, Makefile, Scriping like Perl
Development experience on Linux OS
Knowledge or experience of SystemVerilog
Master degree candidates are preferred
At least 4 days/week for 3 months

How to Apply:
http://my.ericssoncampus.com/Login.aspx?ReturnURL=/job/checkjob.aspx?job_id=136
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