Requirement:    
      -  Good knowledge of design verification methodology.      
      -  Experience on SystemVerilog    
      -  Strong C/C++, Perl, Shell, Makefile.    
      -  Good RTL coding with Verilog.    
          
Working Time:          
      -  Full time, at least 4 days a week          
      -  Long term is mandatory (>=6 months)          
                      
Location:          
      No.2 Science Institute South Rd., Raycom Tower C, HaiDian District, Beijing          

  
Contact: lifeng．chen＠amd.com    
          
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FROM 123.116.149.*