Office Address: 上海市徐汇区桂箐路65号新研大厦B幢12楼
Below are the latest openings for your reference.
If you’d like, you may send the resume to justin.xie.uj@renesas.com, or contact me by QQ: 1652210975
1.Staff Analog Design Engineer --DDR
Location: Shanghai, China
Job Description
o Work with analog and ASIC design team for new product development;
o Work closely with layout designer for layout implementation
o Verification of performance requirements using appropriate simulation and verification tools.
o Support test & product team with chip debugging, failure analysis, characterizations and product release efforts.
Qualification Requirements
o Master degree or above in EE or related field;
o 5+ years of experience on analog IC design area; experience of 40nm or 28nm process preferred,
o Familiar with details of product development: design method, design process, CAD tool, design for test, physical design, system application;
o Strong experience in DDR or high speed projects design, such as SerDes, HDMI, USB 3, PHY and etc.
o Experience in high speed IOs design (Equalizers, Drivers, etc.) or PLL is a plus
o Familiar with CAD tools, such as schematic capture, SPICE simulator (or equivalent transistor level circuit simulator), Virtuoso and Matlab system building;
o Understanding of CMOS process technologies and device physics;
o Good language and communication skills in English for both spoken and written;
o Highly organized and self-motivated;
o Ability to work well with teammates (locally or remotely) in a fast-paced professional environment.
2.Staff Analog Design Engineer –T Sensor
Location: Shanghai, China
Job Description
o Work with analog and ASIC design team for new product development;
o Work closely with layout designer for layout implementation
o Verification of performance requirements using appropriate simulation and verification tools.
o Support test & product team with chip debugging, failure analysis, characterizations and product release efforts.
Qualification Requirements
o Master degree or above in EE or related field;
o 5+ years of experience on analog IC design area:
-Knowledge of Analog and mix-signal design;
-Sigma-delta ADC/ Switch-Capacitor design experience is better;
o Familiar with details of product development: design method, design process, CAD tool, design for test, physical design, system application;
o Familiar with CAD tools, such as schematic capture, SPICE simulator (or equivalent transistor level circuit simulator), Virtuoso and Matlab system building;
o Understanding of CMOS process technologies and device physics;
o Good language and communication skills in English for both spoken and written;
o Highly organized and self-motivated;
o Ability to work well with teammates (locally or remotely) in a fast-paced professional environment.
3.Staff Digital Design Engineer -DDR
Location: Shanghai, China
Job Description
o Work with analog/digital ASIC design team for new product development;
o Design, implementation, and verification of digital in mixed-signal ICs;
o Perform backend digital design (logic synthesis, formal check, define design constraints for place & route, perform timing closure, DFT);
o Support system, test & product team with chip debugging, failure analysis, characterizations and product release efforts.
Qualification Requirements
o Master degree or above in EE or related field;
o At least 5 years’ experience in digital design;
o Have rich experience at high speed digital design;
o Projects tape out experience with 40nm or 28nm preferred;
o Good knowledge in semi-conductor and transistor level;
o Good language and communication skills in English for both spoken and written;
o Highly organized and self-motivated;
o Ability to work well with teammates (locally or remotely) in a fast-paced professional environment.
4.Staff or Sr. Staff Signal Integrity Engineer
Location: Shanghai, China
Responsibilities
o Work with a cutting edge DDR4/5 product design team to simulate, analyze and improve the signal integrity and power integrity performance of chip, package and board.
o Align and trade off the SI/PI design target with cross function team. Support the package, IO buffer and die/package PDN design. Review the SI/PI performance of the die and package design,
o Create simulation bench to perform pre-layout and post-layout simulation of signal integrity and power integrity.
o Extract the S parameter/RLC/TLine model, according to specific accuracy, bandwidth and simulation time requirement.
o Lab measurement to verify the SI/PI performance and trouble shooting.
Qualification
o Minimum BSEE, MSEE preferred;
o 6+ yrs. of experience on signal integrity area;
o Strong knowledge of transmission line theory and electromagnetic field theory, such as reflection, crosstalk, SSN and power noise.
o Experience in signal integrity simulation and analysis on DDR or other multi-loading system is required
o Knowledge of semiconductor package and circuit design. Good understanding of IO buffer architecture and IO analog design is a very strong plus.
o Knowledge of chip/package PDN design.
o Experience in 2D/2.5D/3D model extraction tool, HFSS and Cadence/Sigrity tool is a plus
o Experience in circuit simulator, ADS/Hspice/Spectra is a plus
5.Sr. Staff Verification Engineer
Location: Shanghai, China
Responsibilities
o Understanding the expected functionality of designs.
o Developing verification tests and regression plans based on product specification
o Designing and developing verification environments.
o Running RTL, gate-level and AMS simulations and regressions.
o Code/functional coverage development, analysis and closure.
o
Requirements
o MS in EE/CS/ME.
o Minimum of 8 years’ experience in IC verification.
o Proficiency with System Verilog and the UVM verification methodology.
o Familiarity with VerilogAMS is a plus.
o Basic knowledge of logic and circuit design.
o Good scripting and automation skills (TCL, Perl, Python, makefile, etc.).
o Knowledge of PLLs (especially digital PLLs) -- design and architecture experience is a plus.
o Familiarity with serial interfaces like SPI/I2C/SMBus; I3C is a plus
o Knowledge of AMBA protocols
o Proficiency in oral and written English.
o Independent, proactive and self-managing.
o Good communication and problem-solving skills.
--
FROM 114.88.193.*