联系微信 361261541
以下是多家公司的职位 更新信息欢迎联系
一 北京 soc架构师
工作职责
作为芯片硬件架构师对芯片设计的全生命周期负责；
驱动系统/软件/硬件的协同设计；
执行功耗、性能、面积的性能建模和分析并跟踪设计；
硬件规范编写，审查和系统C模型开发（如果适用）；
审查ASIC，软件和平台中的规范和验证计划，以确保符合要求；
行业标准跟踪和第三方IP技术评估；
与内部团队合作高质量的解决技术问题；
支持硬件/软件启动和调试；
为系统架构的新颖部分申请专利；
工作要求
计算机或电气工程硕士或博士学位；
至少8年的芯片开发或架构工作经验；
对芯片架构定义有很好的了解，包括但不限于-时钟，复位，总线，内存控制器，启动，电源管理，安全性，系统性能，IO技术（PCIE，LPDDR等），CPU一致性，平台集成；
了解建模并具有创建高级模型的能力，以验证系统架构决策并对要求的带宽性能进行评估；
熟悉芯片设计，集成，实施和验证；
在架构定义的各个级别（从微架构到系统级别再到软件架构）进行沟通和解决问题；
出色的分析，书面和口头人际交往能力以及团队合作能力；
加分项
对蜂窝网络以及2G，3G，LTE和5G技术有深入的了解
熟悉相关算法，软件和射频硬件
二、上海 硬件芯片架构系统工程师
工作职责
1. Analysis of Smartphone requirements, mapping of requirements to chipsets, discrete components and development of architectural specifications.
2. Development of Chipset/Discrete-component partition with emphasis on overall product cost, performance, flexibility, scalability and reusability.
3. Definition of chipset interface electrical and logical specifications ensuring consistency and plug & play functionality within product families. Analysis of discrete components, cost, power and performance.
4. Setting targets for and driving bill of materials and cost reduction, and best in class power and user experience.
工作要求
1. MS with 5+ years’ experience in hardware/software system or chipset development for low power wireless SoC and wireless chipset platform development.
2. Understanding of Power & Clock supply architecture for smartphone, LPDDR5/LDDR4x/CSI/DSI/PCIEGen3/USB3.0 interface subsystem requirements and architecture.
3. SOC chip assembling and packaging, system board level design or development.
4. Familiar with the related Modeling and Simulation tools for functionality, SOC performance, power, thermal and others.
5. Familiar with SOC boot process and software kernel development will be perfect.
6. Good team spirit and outstanding written and oral communication.
三、无线系统架构师
工作职责
In this role, you will be in a silicon architecture design team responsible for system, software, digital and analog architecture of connectivity SoCs and applications.
Descriptions
1. Define & document software and hardware architecture for cross-layer (MAC/PHY, PHY/RF, multi-chip) features and functionality.
2. Understanding and mapping of system requirements to ensure development of state-of-the-art design covering all aspects of the system including functionality, performance, power, area, latency, and debuggability.
3. Collaborate with marketing, application development, SoC, MAC, PHY, RF, software and hardware teams to ensure architecture meets the end-to-end system requirements.
4. Drive pre- and post-silicon bring up of state-of-the-art physical/cross-layer wireless communication chips.
工作要求
1. 10+ years relevant experience in software, SoCs, MAC, PHY or RF architecture, algorithm design and simulation, and bringup of wireless SoCs. EECS related MS or Ph.D. education background.
2. Good understanding of the KPIs (performance, power, area, latency, etc) of wireless SoCs and efficient HW architectures to achieve the same.
3. Good understanding of communication theory and standard, as well as implementation.
4. Good understanding of software and digital design and architecture principles.
5. Strong working knowledge of and/or participation in wireless standards such as LTE, 5G, IEEE 802.11a/b/g/n/ac/ax, GNSS, UWB or Bluetooth/BLE.
6. Excellent communication and documentation skills.
7. Ability to develop detailed system architecture and design documentation.
8. Ability to work across cross-functional teams including marketing, product development, digital, analog, RF, verification, software and hardware teams.
四、上海 多媒体硬件架构师
工作职责
Main Responsibilities:
? Lead the team to define ISP pipeline and system architecture, to achieve the best tradeoff of image quality, efficiency (silicon cost, DDR bandwidth, SW complexity), and flexibility.
? Interface with the system architect, SW architect, algorithm team to analyze usecase, build up hardware pipeline, define data flow and data pattern formats, provide estimate of DDR bandwidth, power, latency, and silicon implementation area cost etc.
? Work across teams to define requirement for the fixed-point C-models, assist the microarchitecture design and verification of IP modules.
? Work across teams to develop performance models and power models.
工作要求
Requirements:
? MS/PhD in relevant field (EE, CS), with 8+ years work experience.
? Deep understanding of at least one of the multimedia areas: ISP, camera, video codec, audio codec, mobile display, and AR/VR/CV.
? Understanding of the latest artificial intelligence (AI) technologies for multimedia processing
? Deep understanding of estimation for silicon area, memory bandwidth, power consumption, and the associated firmware complexity.
? Deep understanding of how data storage and movement pattern affect efficiency.
? Familiarity with computer architecture, silicon design, interconnect and bus technologies, and memory hierarchy.
? Excellent communication skills, Fluent in English reading and writing.
五、上海 总线架构
工作职责
负责手机芯片总线架构的规划，针对各mater特点和带宽需求，规划合理的总线架构，满足系统各部分对带宽和时延的需要。配合低功耗架构师实现总线低功耗的规划。 配合ddr的架构师完成整系统的性能优化。配合安全架构师完成总线安全的设计。
工作要求
计算机体系架构方向，微电子专业或其他弱电专业背景。
1，熟悉AXI，AHB，ACE，CHI，OCP，APB等协议，对各种协议有深入理解。 2，对总线调度，仲裁，延时，带宽分配有深刻理解 ，对Qos，urgency，virtual channel等方法深刻理解。对DDR协议有一定程度的熟悉。
3，熟悉ARM的CCI、DSU等模块功能和特点。 4， 熟悉NIC，Noc等总线工具者更佳。
5，曾经主导过一款大型soc总线架构者更佳。
六、基带芯片物理层系统建模架构工程师(ESL系统工程师)
职位描述：
对基带芯片物理层子系统进行建模，包括但不限于内存，互连，硬件加速器，DSP，CPU等。
· 搭建基于TLM(事务级模型)的虚拟平台和ESL仿真环境。
· 为基带数据通路处理中的内存，互连和其他IP编写SystemC TLM模型。
· 创建3GPP物理层各种UE配置和用例下各物理层组件的可配置的随机驱动或任务驱动的负载激励模型。
· 分析性能（吞吐量，延迟，带宽等）和功耗仿真结果。
· 研究设计参数对性能指标的敏感性，并探索改进的体系结构替代方案。
· 和ASIC设计工程师一起制定优化的基带物理层子系统架构。
· 和算法、ASIC、固件以及验证工程师一起验收ESL模型，并根据产品后期数据校准和优化ESL模型。
任职资格：
· 电子工程，计算机工程，通信工程或相关技术领域的学位
· 熟悉C++ / SystemC建模
· 丰富的tcl / tk，python和shell等脚本编程经验
· 熟悉基带芯片系统架构设计
加分项：
· 丰富的高级建模，ESL设计方法和工具经验
· ASIC设计或验证的经验。
· 熟悉Synopsys / Cadence / Mentor设计流程。
· 低功耗设计和功耗分析的经验
七、AI处理器架构
工作职责
1.AI处理器体系结构设计/建模：定义和编写AI处理器规范，领导或进行体系结构仿真，开发模拟器
2.AI处理器架构设计和具体实现（包括C model与RTL）及评估；
3.AI处理器编译器工具、算子的优化与实现
工作要求
1. 计算机/电子等相关专业硕士及以上学历；
2. 熟练掌握数字电路设计与验证；熟悉计算机体系结构；
3. 熟练掌握 C/C++、HDL 语言，熟悉FPGA开发；
4. 熟悉 CPU 或 DSP 设计或参与过 ASIP 设计；
5. 熟悉编译器开发与优化,了解LLVM、TVM；
6. 有AI芯片和工具开发者优先；
八 其他：
CPU系统架构
高速接口
NOC设计/系统架构师
建模及功耗优化架构师
基带芯片物理层系统架构师（处理器评估方向）
片上缓存算法架构师
架构建模工程师
PMIC芯片架构系统工程师
GPU架构师
--
FROM 219.140.142.*