1、专注IC的猎头-katty 微信 361261541
2、手上有数十家公司的IC设计职位: 芯片架构 、数字前端 、 验证、 DFT 、综合、 后端 模拟设计等等。
3、地点:上海 北京 深圳为主,部分西安 合肥 武汉 成都。
4、模拟职位包括不限于以下,如果您具备三年以上模拟设计(各方向),欢迎联系.
以下是多家公司的职位JD:有模拟工程师 、模拟专家、 模拟经理等职位(地点上海)
DDR PHY模拟设计工程师
工作职责
DDR PHY团队目前正在寻找电路设计工程师,他们将直接参与架构设计以及针对最新LPDDR标准的高速数据/时钟路径的系统级分析。
设计目标包括高速Rx / Tx和低功耗电路设计,以提供一流的性能,功率和面积(PPA)解决方案。
1.用于4.2gbps的LPDDR / 4x和6.4gbps的LPDDR5的高速Rx / Tx,时钟和低功耗电路的体系结构和设计。
2.端到端系统时序预算,最佳PPA的权衡和良率设计。
3.详尽的硅前设计验证流程,通道优化,功率传输和信号完整性。
工作要求
1. 5年以上最新技术节点中高速DDR PHY的电路设计经验。 高速Rx / Tx设计技术(如CLTE,DFE,预加重等)和时钟电路。
2.具有高速片外DDR DRAM接口(LPDDR4 / 4x和LPDDR5)的系统级分析经验。
3.深入了解封装和功率输出。
4.具有最新工艺技术节点的经验。
5.具有自定义原理图捕获,布局和SPICE分析的经验。
6.对DDR PHY有良好的理解或架构,系统和集成方面。
7.接触DDR4,LPDDR,GDDR6和宽内存系统。
8.对DDR系统的良率和生产挑战的设计有很好的了解。
9.充分了解JEDEC DDR规格和时序参数。
10.擅长工具: Cadence virtuoso, Spectre, AMS。使用Synopsys的Hspice类似工具。使用Verilog优先。
模拟设计专家
工作职责:
1、负责完成模拟IP的架构设计及规格制定
2、负责完成相关模拟IP模块的建模、设计、仿真、验证和调试工作
3、负责模拟IP模块的关键技术攻关与技术竞争力分析
4、指导完成模拟IP的设计验证、版图规划、系统集成及测试方案等
5、撰写详细的设计文档
岗位要求:
1、微电子及电子类相关专业,本科及以上学历
2、八年以上(硕士)、十年以上(本科)模拟、混合信号 IP 设计经验,熟悉先进工艺下的高速IP设计,至少精通MIPI D-PHY,M-PHY,PCIE,DDR,USB,HDMI,Serdes,PLL等某一个领域
3、熟悉先进工艺节点的芯片设计及开发流程
4、有系统建模能力,有模拟IP行为级建模经验优先
模拟设计专家-上海
岗位描述
The candidate will be the major interface to the IO analog/mixed signal design team or vendor. The candidate will be responsible for defining, implementing, and delivering fully functional and production ready chip IO Serdes infrastructure such as PCIE and DDR PHY, Die-to-Die interconnect. Detailed responsibilities include:
All IOs and analog/mixed-signal hard IPs evaluation, selection and integration.
Work with IP design team/IP vender on design review, quality control, schedule management.
Participate in the IO related physical design, provide IO timing constraints for all related interfaces. Drive the mixed-signal IP integration
Participate in the packaging design and focus on Serdes and Die-to-Die interconnect related issues.
Tape-out review sign-offs, including Serdes PHY, DDRx PHY, PLL, Die-to-Die interconnect, Sensors.
In Silicon bring up, coordinate the effort between system team, silicon team and IP vendors in bring up high speed IO interfaces, debug and resolve IP and hard IP issues
岗位要求
Minimum MSEE with 8+ years or Ph.D. with 5+ years of relevant industry experience.
Deep understanding of mixed signal high speed IO/PAD, DDRx PHY, and Serdes PHY design and architectures
Must have hands-on experience of successful design and tape out high quality IO subsystem, PHY, PLL and another analog IP.
Direct experience in PHY and Serdes bring up, debug and characterization using lab equipment.
Self-driven, excellent problem solving and analytical skills, good communication skills and a strong team player.
Local and international travel may be required.
资深模拟IC设计经理
岗位职责:
1. 搭建公司模拟IC研发团队,对研发团队提供专业的测试支持
2.负责模拟IC产品的架构设计,Spec定义,指导并完成产品的研发
3. 掌握项目进度,推动推对开发步骤;
4. 指导模拟电路的设计与仿真验证,并完成相关文档
6.指导芯片的测试及Debug工作
任职要求:
1.微电子及相关专业,硕士及以上学历,5年以上模拟IC设计经验
2.熟悉并深刻理解CMOS/BCD工艺,了解器件物理、IC制造流程及工艺
3.具有深厚的模拟/混合信号电路设计背景及经验,熟悉数模混合芯片设计的全部流程,具有SOC模拟设计经验更佳
4.具有高速,高精度,低功耗ADC/DAC、高速接口电路或DC/DC、PLL,Bandgap,oscillators等方向流片经验者优先
5.熟悉I/O电路设计,ESD/EOS保护电路设计
资深模拟芯片设计工程师 上海 合肥
职位详情
Performance Objectives
1.Definition, modeling, design, and verification of highly integrated power-management ICs such as DCDC converters, LED drivers, linear regulators, and other types of analog/mixed-signal ASICs.
2.Ability to work at any level of the design is absolutely essential.
3.Implement full-featured behavioral models of complex analog/mixed-signal ICs.
4.Interface with test, product, and applications engineering to drive the design to a successful production release.
5.Provide technical leadership including mentoring less senior members of design team, contract design resources, and layout supervision.
6.Assist in silicon validation and lead troubleshooting efforts to root out unintended circuit behavior through simulation, FIB, and intensive laboratory debugging.
7.Close collaboration with product definition and system architecture groups.
Requirements
1.BS with 5+ years or MS/PhD with 3+ years of analog mixed-signal design experience preferably in the power-management application area.
2.5+ years of analog, mixed-signal IC design experience encompassing diverse areas such as: DC-DC conversion: switch-mode or linear regulators ADC/DAC PLL/CDR Continuous and discrete-time analog integrated filters I/O interfaces Analog test (DFT) interfaces
3.Proven track record of technical leadership including multiple products taken from specification through design, release, volume manufacturing, and field support.
4.Detailed knowledge of power conversion architectures and analytical methods highly desirable.
5.System modeling skills in SIMPLIS or Matlab highly desirable.
6.CAD tools: Must be familiar with Cadence Virtuoso CAD tool suite: schematic, layout, simulation and verification. Must be experienced with top-down analog behavioral modeling methodology including fluent use of Verilog-A/AMS as appropriate. Skill in design automation tools and scripting environments is essential. Familiarity with Verilog and digital design and verification is a plus.
模拟设计部经理
职位责任描述:
整体把握芯片模拟电路架构设计,顶层集成。
根据项目进度制定详细电路设计计划,跟踪设计进度,把控关键参数指标。
根据芯片定义需求,确认模拟电路的模块划分,模拟模块的设计规格书
依据模拟电路设计规格书要求完成模拟模块电路的设计和仿真。
规划模拟电路的测试方案和量产测试设计方案
负责指导版图设计工程师实现模拟电路的版图设计,并完成后仿。
负责与系统和数字电路设计工程师进行接口定义和沟通。
撰写相关设计文档和技术资料。
基本要求:
大学硕士或以上学历,集成电路,微电子学,电子工程,通信等相关专业毕业。
5年以上模拟电路设计经验。
熟悉常用EDA软件,如cadence ADE, calibre, Matlab 等。
熟悉各种常规测试仪表的使用,可独立进行芯片测试和分析测试结果。
具备较强的英语阅读理和书写能力。
沟通能力强,具备团队协作精神,能够承受工作压力。
有团队管理经验者优先
有LCD,OLED驱动电路(DDIC)或高速模拟接口电路设计经验者优先考虑
SerDes工程师
职位描述
负责先进工艺高速SerDes接口电路的设计开发,验证,测试等工作。
具体内容包括:
1,参与SerDes顶层架构的设计建模,各模块spec设定等。
2,负责设计SerDes模块,包括并不限于CTLE/TIA/CDR/DFE/SST driver/Low jitter PLL等。
3,对需要校准的模块给出校准方案,并和数字电路联合仿真验证。
3,指导Layout工程师进行版图设计优化。
4,负责芯片测试,以及文档整理撰写等。
职位要求
1,对SerDes架构有一定的理解,有过3年以上相关设计经验,参与过常用模块的设计。
2,开发过常用SerDes协议,比如Ethernet/PCIE/JESD 204B/204C等。
3,熟悉先进工艺,有过多次流片经验,在Finfet工艺上流片者优先。
4,可以操作常用的测试仪器,高速示波器,频谱分析仪等。
Senior ADC/DAC Engineer:
1.Master degree in electrical engineering with 5 years of experience or more, PhD in electrical engineer with 3 years of experience or more.
2.Strong experience in high Speed ADC/DAC design, must have hands-on tape out experiences of Pipeline, SAR, Sigma-delta ADC.
3.Strong analytical skill and familiar with underline theory for both time domain analysis and frequency domain analysis
4.Solid understanding and experience in key analog layout considerations such as device matching, parasitic, noise coupling, floor planning, sensitive signal routing, current density and reliability considerations.
5.Familiar with both schematic and layout tool, methodologies, flow and CAD tools such as SPICE, Cadence virtuoso, Spectre, PCELL layout, Calibre physical verification.
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