An exciting opportunity has arisen in the Product Development Team for the role of a Design Verification Engineer. The successful applicant will take ownership of all aspects of digital verification for complete IC developments, work on complex verification subsystems and will contribute towards improvements in methodology within the team. This is a fantastic opportunity to work in such an innovative environment, in an organisation operating at the forefront of technology!

Responsibilities

Definition of IC verification plan linking product requirements through to detailed testcases
Create reliable and reusable testbench for complex subsystems and ICs
Participate in verification Expert Groups and contribute to the digital verification methodology discussions
Supporting, and where necessary coaching, the verification team to follow, and improve, defined methodology practices
Hands-on project design/verification involvement
Required Skills and Qualifications

Degree or equivalent in Electronics/Computer Science or other related discipline
Metric driven verification - Verification planning, requirements extraction - Directed and  constrained random verification - Functional and code coverage analysis
Verilog
SystemVerilog - SVA (SystemVerilog Assertions)
Testbench design with verification frameworks like UVM/OVM, e, VMM
Object orientated programming (OOP) - Use of OOP design patterns
Aspect orientated programming (AOP)
Scripting experience with Ruby, sh/csh, TCL, Make, Perl
Debugging skills - RTL - Testbench, OOP - Gate level (including SDF)
Power aware verification (using CPF/UPF)
Formal verification and verification qualification techniques
Strong ability to interpret results and resolve problems
An innovative, creative, lateral thinking problem solver
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修改:feiyingCQ FROM 81.153.188.*
FROM 81.153.188.*