MTS or SMTS – Physical Design (power optimization)
    
    
    
THE ROLE:
    
Power is a more and more hot topic in IC design. We are a power/performance/area optimization Physical Design methodology team.  In this position, you will work with global team especially physical design team for GPU chips physical design power optimization/reduction. Focus on physical design methodology optimization/update to improve chip Power and Performance/Area (PPA), including  RTL -> Syn ->place&route iteration/optimizing. The individual is expected to be an expert in physical design areas, it is a plus to have strong ability in multiple aspects in Front-End or RTL coding experience or Synthesis.  
    
    
    
THE PERSON:
    
Strong self-motivation for technical topics, quick and deep learner, strong communication skill within global engineering team, strong team spirit help and support team members.
    
    
    
KEY RESPONSIBILITIES:
    
Develop/practice state-of-art physical design  methodology
Verify and test the power optimization methodology in physical design flow.
Closely co-work with GPU chip project design team, help/support/drive them adopt the Physical Desing  methodology
    
    
PREFERRED EXPERIENCE:
    
Preferred 6+ years or more years of experience in physical design in digital ASIC chips
Be very familiar with physical design power optimization methodology, (eg. Clock-gating, power-gating, activity aware PnR, power friendly floorplan, DVFS, multibit re-banking de-bandking, scan path power …)
Expert in Back-End (physical design) EDA tools, especially the power calculation/optimization tools,
strong flow develop and custom script develop ability
Knowledgeable in all aspects of deep submicron ASIC design flow
Successfully gone through several complete product development cycles
work well with cross-functional teams
Good listening, writing and speaking English
Good communication skills, strong interpersonal skills and the flexibility
    
    
ACADEMIC CREDENTIALS:
    
preferred MSEE with 8+ years or Bachelor with 10+ years of industrial experience in ASIC design
    
    
LOCATION:
    
Beijing
--
FROM 210.12.100.*