之前伯克利整出来chisel是基于scala.
但是很多人表示spinal HDL更贴近与工程师使用.
学院派的东西阳春白雪,不如实干派的下里巴人.
现在加州大学洛杉矶分校搞出来的这个pygears,跟前面两个争市场
不知道最后能怎么样.
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SystemVerilog is generated by instantiating desired gears and calling PyGears hdlgen function. Here is an example of how this works for the filter gear:

from pygears import gear, Intf
from pygears.typing import Uint
from pygears.hdl import hdlgen

@gear
async def mac(a: Uint['w_a'], b: Uint['w_b']) -> Uint['w_a + w_b']:
    acc = Uint[a.dtype.width + b.dtype.width](0)

    while True:
        async with a as d_a, b as d_b:
            acc += d_a * d_b
            yield acc

@gear
def filter(x, *b, stage=mac):
    y = x
    for bi in b[:-1]:
        y = (y | stage(b=bi)) >> x.dtype

    return y * b[-1]

x = Intf(Uint[16])
b = [Intf(Uint[16])]*4

iout = filter(x, *b)
assert iout.dtype == Uint[32]

hdlgen('/filter', outdir='~/filter_svlib')


看样子是sv.其他例子没有.
【 在 samssmarm (samssmarm) 的大作中提到: 】
: 是不是还要转成verilog?
: 发自「今日水木 on iPhone 13 Pro」
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FROM 223.104.97.*