希望是研二在读的同学，导师能允许来公司实习3~6个月。
感兴趣的同学请站内联系。

Job Descriptions:
Responsibilities
o    Understand RTL design specification and verification plan
o    Develop verification testbench components and stimulus
o    Analyze and conclude root cause for issues and failures
o    Implement new flows and methodologies

Requirements
o    Bachelor or master’s degree in Microelectronics, Computer Science or relevant disciplines
o    Good knowledge on typical IC design flow
o    Good knowledge on Verilog, C/C++ and scripting languages (Perl, Python, etc.)
o    Experience on using simulator (VCS/Questasim/IUS) and debug tool (Verdi)
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FROM 113.208.115.*