AMD上海正在招聘 Silicon Design Engineer，请有意向者联系Cherry.Zhang@amd.com

AMD System Management Unit(SMU) IP team delivers differentiated system management IP for all AMD products. You'll be working with the global team on complicated clock scheme, security processing, network on chip, power management, etc.


RESPONSIBILITIES:

The successful candidate will assume technical leadership of a complex design generally including custom digital logic, an embedded u-controller and analog functionality. The following is a list of key responsibilities that the candidate will assume:
Responsbile for architecture and micro-architecture definition
Digital design and RTL coding.
Co-ordinating design verification activities.
Co-ordinating front-end and physical implementation activities

REQUIREMENTS:

Minimum 5-6 years of experience with Verilog a MUST
Excellent knowledge of verilog, C, C++ and a scripting language; experience with Perl and TCL is a plus
Experience with low level, physical phenomena oriented logic design is an asset (dealing with IO, clocking, voltage control, DFT, etc.)
Power/thermal management experience is an asset.
Experience in industry standard IO IPs - SPI/I2C/SMBUS/USB/PCIE is a big plus
Embedded micro-processor experience is a plus
Security/cryptography experience is an asset
Strong analytical/problem solving skills and pronounced attention to details.
Must be a self starter, and able to independently drive tasks to completion.
Strong interpersonal and communication skills

EDUCATION:

Bachelor, Master's or PhD degree in Electrical or Computer engineering.
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