NVIDIA英伟达超多芯片岗位来袭！！
加入NV的N个理由:
1. GPU，人工智能和自动驾驶的全球领导企业, 过去3年, 股票走势强劲
2. 能够直接参与到最先进,最复杂的芯片项目中, 业界最好的工具, 几百万的硬件加速平台任你用
3. 崇尚工程师文化, 重视员工职业发展, 技术岗位的管理岗97%从内部提拔
4. 技术领先, 参与制定众多的行业标准, 同时公司鼓励创新, 鼓励内部流动，从不限制员工发展
芯片岗位
1. ASIC PD Engineer (时序/综合)-上海
2. Physical Design Engineer (后端)-上海 北京 新竹
3. Circuit Design Engineer (CAD)-上海
4. Layout Design Engineer-上海
5. DFT Engineer-上海/台北
如何加入我们:
工作经验不限, 岗位职级Open, 详细职位描写如下, 欢迎大家投递简历：tracyw@nvidia.com
WeChat: 1751315121
ASIC Physical Design团队-上海
我们是谁:
全球团队中的核心团队，NVIDIA上海ASIC-PD团队是除美国总部之外最大的海外团队，团队已经独立完成了数十块芯片的物理整合和时序分析，技术覆盖所有的角落，水平在全球团队中处于领先地位。
作为ASIC-PD的成员，会负责GPU和Tegra产品线的研发，与IP，DFT，PR，Library等各团队紧密合作，完成从RTL freeze到tape out的芯片实现。高品质按计划完成芯片网表，constraint的release。工作内容还包括各模式各层次各corner的时序分析修复，sign off，对流程的优化和改进，以及对新工艺的研究和使用。
关键词:
Synthesis Formal check
Design quality check
Partition
Constraint
Timing corner definition Timing analysis/closure
Timing signoff
Async check: CDC/MTBF/Glitch/reconvergence/async timing.
Lib quality check
Methodology
在这里你可以
1. 参与世界上几乎最大最先进的芯片物理设计，有机会接触了解到从前端设计到后端流片的各个环节，学习最领先的芯片设计知识和方法。
2. 应用多级hierarchical物理设计技术完成超大规模芯片设计。
3. 应用最先进的工艺：选择corner，研究和定义不同corner的参数：ocv，derating，setup/hold margin。
4. 负责最先进的超高速IO物理实现：不仅仅是了解设计，加约束，写流程，收敛时序；还需要预测下一代的时序问题，提出解决方案。
- 27G GDDR物理设计
- CXL/NVLINK 物理设计：最新高速计算数据接口
5. 学习CDC，异步时序设计，异步设计失效是很难检测的失效，多数公司却没有完整的解决方案。
6. 面对最有挑战的芯片设计问题，与ASIC，ANALOG，P&R等设计者紧密合作解决相关问题；技术能力，交流沟通能力，以及团队合作解决复杂问题的能力都能得到充分的发挥和提高。
7. 在完成设计的同时完善流程，提高工作效率，把重复的工作交给工具，把自己的时间集中在有挑战的工作上面。
欢迎这样的你加入我们
1. 微电子、电子工程、计算机等相关专业学士以及以上学位
2. 对静态时序分析，综合，网表质量检查，形式验证，CDC，异步时序分析等的全部和部分有良好的了解，有相关工作经验。
3. 良好的团队合作精神和解决问题的能力
5. 掌握一定的脚本知识，如perl，python，tcl，csh等
6. P&R, ASIC design and DFT etc. knowledge is a plus.
和他们并肩作战
团队有很多20年左右经验丰富的高级工程师，有各个方面的技术专家。我们不但知道怎么做，而且知道为什么这么做，还一直在争取做得更好更容易的路上
Physical Design Engineer (后端)
部门简介：
上海VLSI Physical Design 部门成立于2005年， 在过去的15年里，我们成功地参与并设计了NVIDIA发布的所有产品。我们使用的是最前沿的生产工艺，最先进的EDA工具以及最复杂的设计流程。致力于最先进的产品设计，挑战技术之巅是我们一贯的追求。
【你会做些什么】
负责NVIDIA (英伟达)公司所有芯片（包括GeForce，Tegra，Tesla，Quadro等系列）的物理设计及其实现（Netlist to GDSII）， 以及流程开发（Flow development）。
致力于：
芯片规划及布局, 顶层设计到底层模块的划分
电源/时钟分布及规划
布局布线 (包含从顶层设计以及底层模块的全部内容)
静态时序/功耗/噪声/可制造性优化及分析
物理验证
流程自动化以及回归测试
与EDA提供商合作进行工具评估和改进
开发内部工具和解决方案
【我们想要看到这样的你】
微电子, 电子工程及相关专业硕士生
有相关课程背景：集成电路设计, 数字电路设计, 半导体器件
有以下知识：芯片设计, 布局布线
有数字芯片项目设计经验或者使用ASIC设计流程的经验优先
有EDA工具（布局布线，时序分析，电路仿真, 版图设计等）的使用经验优先
有使用Perl，Tcl，Python和Shell等语言编写脚本的能力优
Circuit Design Engineer (CAD)-上海
We are now looking for a CAD/Methodology Engineer for custom circuit design, to develop and maintain design methodologies, flows for high-performance low-power circuit design, contribute to NVIDIA's state-of-the-art products.
What you’ll be doing:
Develop design methodologies, tools, and flows for custom circuit design and verification
Support full custom design flow from schematic to GDSII
Internal CAD tool development, EDA tools integration, for simulation and physical verification
maintain custom circuit design environment and tools
What we need to see:
BS or above, major in EE/CS or equivalent experience
1+ years of practical experience
Good programming skills, experience in Perl/Shell/Tcl/Python is preferred
Good knowledge in deep submicron CMOS process and device
Familiar with circuit design tools and custom design flow
Experience in design/verification flow automation is a plus
Experience in physical verification tools like ICV/Calibre is a plus
Knowledge/experience in VXL/PCELL/CDF/SKILL language/netlisting/ is a plus
Must be a team player with effective written and verbal communication skills
Must be able to learn quickly and work independently
Layout Design Engineer
We are now looking for Mask Design Engineer for Digital IP team. The team develops the high performance digital IPs used in our chips. The main role is layout design for SRAM, ROM and STDcell using the most advanced IC process in the world.
What you’ll be doing:
Develop digital IP layouts with excellent PPA in the most advanced process node
Verify the layout in cell level and macro level
Maintain the layouts per requests from circuit designers or other internal customers
Create tools or scripts to improve work efficiency
What we need to see:
BS/MS in EE or equivalent experience
Fundamental knowledge in digital logic, semiconductor device and manufacturing process
Minimum 2 years working experience on digital or mixed-signal layout design
Familiar with Cadence design environment and ICV/Calibre verification tools
Excellent communication in English
DFT Engineer-上海
Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.
What you’ll be doing:
You'll be responsible for DFT verification environment setup, own DFT verification and bringup tasks for Clocks, Boundary Scan, Analog, MBIST, Scan, etc. You'll have chance to take the lead role for DFT verifications and bringup.
In long term, you can be a DFT lead for verification or extend the expertise to DFT design or methodology.
What we need to see:
o BSEE with 3+, MSEE with 2+ years of experience or PhD or equivalent working experinece in DFT or design verification.
o Good understanding on ASIC design and verification.
o Hands on experience on at least one DFT feature: Boundary Scan, 1500, MBIST, Scan, ATPG.
o Experience in silicon debug and bring-up on the ATE is a plus.
o Good exposure to clock design, timing/STA, place-n-route or power is a plus.
o Excellent analytical skills in verification and debug.
o Strong programming and scripting skills in Perl, Python or Tcl desired.
o Excellent written and oral communication skills in English with the curiosity to work on challenges.
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