NVIDIA英伟达热招DFT Engineer

加入NV的N个理由:
1.    GPU，人工智能和自动驾驶的全球领导企业, 过去3年, 股票走势强劲
2.    能够直接参与到最先进,最复杂的芯片项目中, 业界最好的工具, 几百万的硬件加速平台任你用
3.    崇尚工程师文化, 重视员工职业发展, 技术岗位的管理岗97%从内部提拔
4.    技术领先, 参与制定众多的行业标准, 同时公司鼓励创新, 鼓励内部流动，从不限制员工发展


如何加入我们:
工作经验不限, 岗位职级Open, 详细职位描写如下, 欢迎大家投递简历：tracyw@nvidia.com
WeChat: 1751315121


DFT Engineer-上海
Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.
What you’ll be doing:
You'll be responsible for DFT verification environment setup, own DFT verification and bringup tasks for Clocks, Boundary Scan, Analog, MBIST, Scan, etc. You'll have chance to take the lead role for DFT verifications and bringup.
In long term, you can be a DFT lead for verification or extend the expertise to DFT design or methodology.

What we need to see:
o    BSEE with 3+, MSEE with 2+ years of experience or PhD or equivalent working experinece in DFT or design verification.
o    Good understanding on ASIC design and verification.
o    Hands on experience on at least one DFT feature: Boundary Scan, 1500, MBIST, Scan, ATPG.
o    Experience in silicon debug and bring-up on the ATE is a plus.
o    Good exposure to clock design, timing/STA, place-n-route or power is a plus.
o    Excellent analytical skills in verification and debug.
o    Strong programming and scripting skills in Perl, Python or Tcl desired.
o    Excellent written and oral communication skills in English with the curiosity to work on challenges.
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