Job Summary
As a member of the core backend team, you will be responsible for the physical implementation (from netlist to tapeout) of a highly complex SOC utilizing state of the art process technology.
Description
o Work with FE team to understand chip architecture and drive physical aspects early in design cycle.
o Design automation; Construct, Guide, Modify, Enhance Timing tools and flows.
o Top level floorplan, partition floorpan, P&R, timing and physical sign off.
Key Qualification
o The ideal candidate will have a minimum of 3 years of physical design experience, with recent successful tapeouts in deep sub-micron technology.
o Expert in top /block level P&R implementation, including floorplanning, clock & power distribution, timing closure, physical & electrical verification.
o Experienced in industry standard tools, understand their capabilities and underlying algorithms.
o Strong communication skills.
o Familiar with sub-micro Synthesis, PR and power sign off tool is a plus.
o Experience with DDR, PCIE is a plus.
o Strong scripting abilities in Python are needed; TCL or Makefile is a plus.
o Experience in methodology of Technology under 16nm is a plus.
o Experience in large - scale chip design is a plus.
Education
BS/MS CE or EE.
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FROM 101.254.121.*