问题现象是：
1. zynq长时间运行后，网口无法ping通；(网卡设置的是固定IP地址)
2. 系统没有死掉，因为自己写的应用程序还在正常运行（通过串口终端观察到的）；
3. 通过串口终端，将网卡ifconfig down后，再ifconfg up后，串口打印信息显示，已经建立连接，但是依然ping不通；
4. 将zynq系统reboot以后，网卡就可以ping通了；
使用的是Vivado 2019.1版本，使用了xilinx提供的axi_ethernet IP
通过petalinux构造的系统
网卡的phy芯片型号为：RTL8211FI-CG
Vivado工程的系统框图在附件中
system-user.dts文件内容如下：
include/ "system-conf.dtsi"
/ {
leds {
compatible = "gpio-leds";
gpio-led3 {
label = "ps_led0";
gpios = <&gpio0 0 1>;
default-state = "on";
};
gpio-led4 {
label = "ps_led1";
gpios = <&gpio0 9 1>;
default-state = "on";
};
};
usb_phy0: phy0 {
compatible = "ulpi-phy";
#phy-cells = <0>;
reg = <0xe0002000 0x1000>;
view-port = <0x170>;
drv-vbus;
};
usb_phy1: phy1 {
compatible = "ulpi-phy";
#phy-cells = <0>;
reg = <0xe0003000 0x1000>;
view-port = <0x170>;
drv-vbus;
};
};
&axi_ethernet_0 {
local-mac-address = [00 0a 35 00 22 01];
xlnx,phy-type = <0x8>;
phy-handle = <&phy1>;
xlnx,has-mdio = <0x1>;
phy-mode = "rgmii";
mdio {
phy1: phy@1 {
device_type = "ethernet-phy";
reg = <1>;
};
};
};
&axi_ethernet_1 {
local-mac-address = [00 0a 35 00 22 02];
xlnx,phy-type = <0x8>;
phy-handle = <&phy2>;
xlnx,has-mdio = <0x1>;
phy-mode = "rgmii";
mdio {
phy2: phy@1 {
device_type = "ethernet-phy";
reg = <1>;
};
};
};
&i2c0 {
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
status = "ok";
};
};
&usb0 {
dr_mode = "otg";
usb-phy = <&usb_phy0>;
};
&usb1 {
dr_mode = "host";
usb-phy = <&usb_phy1>;
};
pl.dtsi的文件内容如下：
/*
* CAUTION: This file is automatically generated by Xilinx.
* Version:
* Today is: Tue Jul 25 08:38:26 2023
*/
/ {
amba_pl: amba_pl {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges ;
axi_chip2chip_0: axi_chip2chip@50000000 {
clock-names = "s_aclk", "idelay_ref_clk", "axi_c2c_phy_clk", "axi_c2c_selio_rx_clk_in";
clocks = <&clkc 15>, <&clkc 17>, <&clkc 15>, <&misc_clk_0>;
compatible = "xlnx,axi-chip2chip-5.0";
reg = <0x50000000 0x10000000>;
xlnx,aurora-width = <0x1000>;
xlnx,axi-addr-width = <0x20>;
xlnx,axi-brst-width = <0x2>;
xlnx,axi-bus-type = <0x0>;
xlnx,axi-data-width = <0x20>;
xlnx,axi-id-width = <0x1>;
xlnx,axi-len-width = <0x8>;
xlnx,axi-lite-addr-width = <0x20>;
xlnx,axi-lite-data-width = <0x20>;
xlnx,axi-lite-prot-width = <0x2>;
xlnx,axi-lite-resp-width = <0x2>;
xlnx,axi-lite-stb-width = <0x4>;
xlnx,axi-resp-width = <0x2>;
xlnx,axi-size-width = <0x3>;
xlnx,axi-stb-width = <0x4>;
xlnx,axi-wuser-width = <0x1>;
xlnx,common-clk = <0x0>;
xlnx,disable-clk-shift = <0x0>;
xlnx,disable-deskew = <0x0>;
xlnx,ecc-enable = <0x1>;
xlnx,en-axi-link-hndlr = <0x1>;
xlnx,en-legacy-mode = <0x0>;
xlnx,include-axilite = <0x0>;
xlnx,interface-mode = <0x2>;
xlnx,interface-type = <0x1>;
xlnx,interrupt-width = <0x4>;
xlnx,master-fpga = <0x1>;
xlnx,num-of-io = <0x14>;
xlnx,selectio-phy-clk = <0x64>;
xlnx,simulation = <0x0>;
xlnx,support-narrowburst = "axi_c2c";
xlnx,use-diff-clk = <0x0>;
xlnx,use-diff-io = <0x0>;
};
misc_clk_0: misc_clk_0 {
#clock-cells = <0>;
clock-frequency = <100000000>;
compatible = "fixed-clock";
};
axi_dma_0: dma@40410000 {
#dma-cells = <1>;
axistream-connected = <&axi_ethernet_0>;
axistream-control-connected = <&axi_ethernet_0>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <&clkc 15>, <&clkc 15>, <&clkc 15>, <&clkc 15>;
compatible = "xlnx,eth-dma";
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <&intc>;
interrupts = <0 31 4 0 32 4>;
reg = <0x40410000 0x10000>;
};
axi_ethernet_0: ethernet@41000000 {
axistream-connected = <&axi_dma_0>;
axistream-control-connected = <&axi_dma_0>;
clock-frequency = <100000000>;
clock-names = "s_axi_lite_clk", "axis_clk", "gtx_clk", "ref_clk";
clocks = <&clkc 15>, <&clkc 15>, <&clkc 16>, <&clkc 17>;
compatible = "xlnx,axi-ethernet-7.1", "xlnx,axi-ethernet-1.00.a";
device_type = "network";
interrupt-names = "mac_irq", "interrupt";
interrupt-parent = <&intc>;
interrupts = <0 29 1 0 30 4>;
local-mac-address = [00 0a 35 00 00 00];
phy-mode = "rgmii";
reg = <0x41000000 0x10000>;
xlnx = <0x0>;
xlnx,axiliteclkrate = <0x0>;
xlnx,axisclkrate = <0x0>;
xlnx,clockselection = <0x0>;
xlnx,enableasyncsgmii = <0x0>;
xlnx,gt-type = <0x0>;
xlnx,gtinex = <0x0>;
xlnx,gtlocation = <0x0>;
xlnx,gtrefclksrc = <0x0>;
xlnx,instantiatebitslice0 = <0x0>;
xlnx,phy-type = <0x3>;
xlnx,phyaddr = <0x1>;
xlnx,phyrst-board-interface-dummy-port = <0x0>;
xlnx,rable = <0x0>;
xlnx,rxcsum = <0x0>;
xlnx,rxlane0-placement = <0x0>;
xlnx,rxlane1-placement = <0x0>;
xlnx,rxmem = <0x1000>;
xlnx,rxnibblebitslice0used = <0x0>;
xlnx,tx-in-upper-nibble = <0x1>;
xlnx,txcsum = <0x0>;
xlnx,txlane0-placement = <0x0>;
xlnx,txlane1-placement = <0x0>;
axi_ethernet_0_mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
};
};
axi_ethernet_1: ethernet@41010000 {
axistream-connected = <&axi_ethernet_1_dma>;
axistream-control-connected = <&axi_ethernet_1_dma>;
clock-frequency = <100000000>;
clock-names = "s_axi_lite_clk", "axis_clk", "gtx_clk", "gtx_clk90";
clocks = <&clkc 15>, <&clkc 15>, <&misc_clk_1>, <&misc_clk_1>;
compatible = "xlnx,axi-ethernet-7.1", "xlnx,axi-ethernet-1.00.a";
device_type = "network";
interrupt-names = "mac_irq", "interrupt";
interrupt-parent = <&intc>;
interrupts = <0 33 1 0 34 4>;
local-mac-address = [00 0a 35 00 00 01];
phy-mode = "rgmii";
reg = <0x41010000 0x10000>;
xlnx = <0x0>;
xlnx,axiliteclkrate = <0x0>;
xlnx,axisclkrate = <0x0>;
xlnx,clockselection = <0x0>;
xlnx,enableasyncsgmii = <0x0>;
xlnx,gt-type = <0x0>;
xlnx,gtinex = <0x0>;
xlnx,gtlocation = <0x0>;
xlnx,gtrefclksrc = <0x0>;
xlnx,include-dre ;
xlnx,instantiatebitslice0 = <0x0>;
xlnx,phy-type = <0x3>;
xlnx,phyaddr = <0x1>;
xlnx,phyrst-board-interface-dummy-port = <0x0>;
xlnx,rable = <0x0>;
xlnx,rxcsum = <0x0>;
xlnx,rxlane0-placement = <0x0>;
xlnx,rxlane1-placement = <0x0>;
xlnx,rxmem = <0x1000>;
xlnx,rxnibblebitslice0used = <0x0>;
xlnx,tx-in-upper-nibble = <0x1>;
xlnx,txcsum = <0x0>;
xlnx,txlane0-placement = <0x0>;
xlnx,txlane1-placement = <0x0>;
axi_ethernet_1_mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
};
};
misc_clk_1: misc_clk_1 {
#clock-cells = <0>;
clock-frequency = <125000000>;
compatible = "fixed-clock";
};
axi_ethernet_1_dma: dma@40400000 {
#dma-cells = <1>;
axistream-connected = <&axi_ethernet_1>;
axistream-control-connected = <&axi_ethernet_1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <&clkc 15>, <&clkc 15>, <&clkc 15>, <&clkc 15>;
compatible = "xlnx,eth-dma";
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <&intc>;
interrupts = <0 35 4 0 36 4>;
reg = <0x40400000 0x10000>;
xlnx,include-dre ;
};
axi_gpio_0: gpio@41200000 {
#gpio-cells = <3>;
clock-names = "s_axi_aclk";
clocks = <&clkc 15>;
compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a";
gpio-controller ;
reg = <0x41200000 0x10000>;
xlnx,all-inputs = <0x1>;
xlnx,all-inputs-2 = <0x0>;
xlnx,all-outputs = <0x0>;
xlnx,all-outputs-2 = <0x0>;
xlnx,dout-default = <0x00000000>;
xlnx,dout-default-2 = <0x00000000>;
xlnx,gpio-width = <0x3>;
xlnx,gpio2-width = <0x20>;
xlnx,interrupt-present = <0x0>;
xlnx,is-dual = <0x0>;
xlnx,tri-default = <0xFFFFFFFF>;
xlnx,tri-default-2 = <0xFFFFFFFF>;
};
};
};
附件(138.6KB) design_1.pdf--
FROM 111.204.124.*