Responsibilities
o    Responsible for defining and developing digital PLL architecture based on product spec.
o    Responsible for digital design including RTL coding, verification/simulation, synthesis, static timing analysis, scan insertion and test pattern generation
o    Overseeing automatic place and route
o    Validating/debugging of silicon

Requirements
o    Bachelors with 5+ years, or masters with 3+ years of experience in digital and mixed signal IC design.
o    Experience of mix-signal IC design with an emphasis on digital flow.
o    Experience in behavioral models of analog circuits and mixed mode simulation.
o    Experience in PLL design is a plus.
o    Experience in silicon validation in the lab with spectrum analyzers, oscilloscopes, signal generators, and etc
o    Familiarity with the design and use of IP blocks like SPI, I2C, I3C, SMBus, EEPROM, and OTP.
o    Experience with Cadence and/or Synopsys design tools
o    Experience with verilog-HDL, SystemVerilog, UVM
o    Familiarity with Perl, TCL, Python and/or C++ scripting
o    Experience in system level modeling and analysis with C/Matlab/MathCad is a plus
o    Experience with design prototyping and validation in FPGA is a plus
o    Good writing and communication skills
o    Be innovative
Keywords
Digital and mixed signal IC design, PLL design, high speed design
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