NVIDIA英伟达招聘DFT Intern(面向2012届应届生)
工作地点:上海
请感兴趣的同学投递简历到monlin@nvidia.com.
此职位面向2012届毕业生,实习表现优秀可通过校园招聘转正。
DFT Engineer(Intern)
Job description:
Design for Testability (DFT) has become a big challenge to VLSI and SOC design
as a result of the unprecedented levels of design complexity and advanced man
ufacturing technologies. Effective and high quality testing is extremely impor
tant for IC products especially the high end products. DFT is a must to guaran
tee high quality of testing hence high quality and reliability of IC products.
Moreover, DFT is a significant method to reduce test cost. Nowadays, DFT is a
lso required to provide useful means for debug and diagnosis at chip/board/sys
tem level, which is Design for Debug and Diagnosis (DFD).
DFT Engineers are important for IC designs to guarantee high quality/reliabili
ty of IC products. As a DFT Engineer, he/she needs to understand various DFT f
eatures such as SCAN/BIST/JTAG and so on and make an appropriate DFT plan for
a design by considering testability, test costs and overhead of DFT logic. The
n, DFT logic as part of the DFT features needs to be implemented and verified
at the proper design stages. DFT test patterns are delivered for ATE chip brin
gup and production test after chip tapeout. DFT Engineer has to work closely w
ith both frond-end and back-end designers to implement DFT logic so that DFT E
ngineer should have deep understanding of the entire design flow, covering the
knowledge of RTL design, verification, synthesis, timing analysis and P&R. In
addition, DFT Engineer also needs to work with test engineer for ATE chip bri
ngup and silicon debug.
We are looking for candidates of DFT Engineer who will be
Responsible for DFT feature implementation and verification
Developing testbench and test procedures/scripts
Verifying Clock, Analog, JTAG, Boundary Scan, MBIST, Scan/ATPG, etc.
Generating test vectors and doing post silicon validation
Improving dft implementation and verification flow
Requirements:
MSEE
Strong logic design and verification background
Possess basic knowledge of DFT (Scan/ATPG, MBIST, JTAG, etc.)
Skilled in Perl/tcl programming
Proficient at Verilog HDL
Prefer to have experience with logic simulators and debug tools (such as vcs,
ncsim, verdi)
Familiar with C/C++, Makefile is a plus
Strong problem solving and analytical skills
Excellent communication skills and teamwork
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FROM 203.18.50.*