【 以下文字转载自 METech 讨论区 】
发信人: janefeier (Forget it!), 信区: METech
标  题: AMD上海Design/Integration 实习生一名
发信站: 水木社区 (Mon Apr  9 13:13:25 2012), 站内


AMD 上海研发中心， FCH部门现招聘一名SOC integration intern, 有过一定的IC design/flow 知识和经验的研一或者研二学生。最好一周5天能工作。该项目是AMD APU的一个项目，在此可以学习到很多AMD APU相关技术。


Position Title     SOC Integration Engineer Intern
Organization    Shanghai R&D Center
Department    FCH (Chipset)
Location             Shanghai, China
Team             SOC integration team

Job Description:      
•    Integrate functional IPs into SoC per architectural requirement, assist senior/staff engineer on flow tasks below which would be a good opportunity to learn from AMD’s APU project.
•    Develop RTL code for macro blocks in Verilog HDL and make sure functional correct and reusable for different configuration.
•    Participate in making functional/technology based chip targets in timing, area, power.
•    Synthesis and deliver qualified netlist, co-work with PD(Physical design team) to settle chip floorplan and achieve timing closure.

Requirement and Preferred Experience:
•    Major in EE, CS or related, postgraduate student.
•    Familiar with ASIC RTL2netlist flows (Leda, CDC, logic synthesis, STA, formality check, ECO, Low Power) and usage of related EDA tools, or some of them.
•    Familiar with script languages ((tcl, perl etc.) in unix/linux.
•    Good written and spoken English.
•    Have enough time and prefer to have 5 working days available per week.


可发信： jane-feier@163.com (本人系本部门员工，不希望工作邮箱收到很多广告特留此邮箱， 您也可站内回信)
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