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Position: ASIC Intern
Location: Shanghai

Job Description/Qualifications:
RESPONSIBILITIES:
- RTL design, verification, synthesis for various low power control logic in
GPU/Tegra chips.
- Develop and maintain verification environment at both full chip & unit
level
- Code/functional coverage analysis
- Responsible for running both RTL & gate level simulation
- Develop testing and regression methodologies
- Develop/maintain/enhance environment tools/scripts/makefiles

MINIMUM REQUIREMENTS:
- In school student, For master or doctor degree in ASIC design or
verification
- Basic Knowledge for Verilog
- Basic Knowledge for C/C++, Makefile
- Basic programming skills or Scripting language: TCL, Perl, Python
- Have at least 3 available working days for every week in the future 6+
months.
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FROM 203.18.50.*