Job Title: [Synopsys] EDA Software Testing tool Developer Intern
Department: Implementation Group / Product Validation team
Location: Shanghai, Zhongshan Park.

Description:  
The basic digital implementation flow relies on 2 EDA tools: Design Compiler  

(DC) and IC Compiler (ICC). DC is used to do logic synthesize (ie. RTL  
Verilog to netlist Verilog) and ICC is used to do physical implementation of  

the chip (ie. Design planning, place, clock tree synthesize and route). The  
netlist Verilog is a must input to ICC. The variance of the netlist Verilog  
is important to test the functionality of ICC.  
Intern’s job is to develop a DC-based design generator. The generator will  
use DC commands, read in some user predefined modules and connect these  
modules with random logics, but respecting to design rules or user’s rules (

ie. Data-path / Clock-path rules, timing loop rules, etc). The primary  
customer of this tool is the ICC validation team in the company.

Requirements:
1.    Strong Background on Digital Integrated circuit (Combinational +  
Sequential)
2.    Strong scripting skill
3.    Understand netlist Verilog and can write it manually
4.    Eager to study and good communication skill
Nice to have (Not a must):
1.    Tcl scripting language
2.    Knowing Design Compiler
3.    Knowing SDC (Synopsys Design Constraints)
What Intern can learn from this internship:
1.    Practice on EDA leading tools (DC, ICC). Practice on logic synthesize  
flow.
2.    Different industrial design styles
3.    Basic digital implementation flow
4.    Programming skills
5.    Work with experienced engineers

除了上面的Intern，IG组还要招一个全职的测DC的工程师，待遇优厚。欢迎来投，欲投
从速，中英名简历（一定要有英语简历，要不录入不了系统）。
邮箱：jyqi@synopsys.com title:[DC Intern] | [DC Full-time]  

有疑问发信到上面邮箱咨询。
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FROM 202.106.180.*