时间安排： 4-5天/周，至少持续6个月-12个月

要求微电子/EE/半导体/CS等相关专业硕士/博士，2015年及以后毕业优先。

投递简历时请注明所投递职位，简历投递邮箱cecilyl@cadence.com

1. Intern - Product Engineer (2 vacancies)

Position Description:
1. Assist in digital reference flow development and optimization at advance
nodes.
2. Be responsible for developing Perl/Tcl scripts for flow data post-
processing, output analysis, etc.
3. Be responsible for various scripting and system development techniques
for high productivity and efficiency.

Position Requirements:
1. MS or excellent undergraduate, EE or CS background.
2. Strong Tcl/Perl programming experience.
3. IC design knowledge and statistic timing analysis knowledge is a plus.
4. Unix System knowledge, vi/TK/CSH will be a strong plus.
5. Good communication in English and Chinese, good self-motivation and
strong willing to learn new technologies





2. Intern - PVS/Assura rule deck development

Position Description:
Work in Cadence China Foundry Access Team, to assist in PVS/Assura rule deck
development and qualification
1. Create test case with Virtuoso Layout for rule deck testing.
2. Develop various scripting for automatic test case generation flow and
automatic QA flow.
3. Assist in rule deck development.

Position Requirements:
1. MS or excellent undergraduate, EE background. Semiconductor process
knowledge is a must.
2. Layout experience with Virtuoso or other tools is a strong plus.
Knowledge in DRC and LVS is preferred.
3. Linux System knowledge, vi/C shell/TCL/Perl will be a strong plus.
4. Good communication in English and Chinese, good self-motivation and
strong willing to learn.




3. PV Interns – Replacement(2 vacancies)


Job description:
1. Work with PV regression team for daily yellow and full QA review
2. Help PV team to deliver some system scripts (by perl/csh)

Position Requirements:            
1. MS or excellent undergraduate, Strong perl programming experience
2. IC design knowledge is necessary, such as statistic timing analysis
3. Unix System knowledge, vi/TCL/TK/CSH will be plus
4. Good communication in English and Chinese, good confidence and good self-
motivation
5. Can work 4 days/week and last for at least 6 months




4. PV Intern for STA

Job description:
This intern will work in Encounter Timing Analysis Product Validation team.
The responsibilities include:
a) Assist in EDI STA result validation
b) Validate and maintain comprehensive STA unit and flow test cases for
Encounter Digital Implementation System.
c) Qualify new STA features

Position Requirements:
a) MS or excellent undergraduate
b) Digital IC design knowledge is necessary; statistic timing analysis
knowledge is a strong plus
c) Unix System knowledge, vi/TCL/TK/CSH/Perl will be plus.
d) Good communication in English and Chinese, good confidence and self-
motivation.
e) Commitment to work as intern for at least 6 months
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FROM 192.203.57.*