【 以下文字转载自 Career_Campus 讨论区 】
发信人: MonserLin (Monser), 信区: Career_Campus
标  题: 【上海全职】NVIDIA急招Power Methodology Engineer(低功耗)！
发信站: 水木社区 (Wed Dec 24 16:11:51 2014), 站内

简历发送至HR(Yvette SHEN)邮箱:yvettes@nvidia.com;

上海研发中心地址：上海申江路5709号（秋月路26号）矽岸国际2号楼

Power Methodology Engineer

Power methodology team is responsible for researching power expenditures and
workload efficiency to identify architectural, micro-architectural
strategies to improve power efficiency of the next generation GPU and TEGRA
chips.

Responsibilities:
1.Develop the power flow to automate the power expenditures measurement.
2.Evaluate new low-power technologies and provide feedback to power ARCH
team to improve chip power efficiency on architectural level.
3.Support GPU/TEGRA RTL designers using the power flow to do the power
scrubbing work and improve their power efficiency on micro-arch level.
4. Understand and perform block level and chip-level power analysis.

Requirements:
1.Familiar with advanced low power techniques and high speed clocking
desired.
2. Experience in low power ASIC design/verification.
3. Programming languages: Strong Verilog (or VHDL), Perl, Tcl is must,  C ++
is a plus.
4.Tool Familiarity: PTPX, Synopsys Design Compiler, VCS simulation tool is
must, Power Artist is a plus.
5.Excellent communication skills and ability to be good at teamwork.
6.Excellent English writing/speaking skills.
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FROM 203.18.50.*