【NVIDIA社招】英伟达上海急招Methodology Engineer
一．公司简介
        NVIDIA (英伟达™)(www.nvidia.cn)公司(纳斯达克代码：NVDA)是全球视觉计
算技术的行业领袖及GPU(图形处理器)的发明者。作为高性能处理器的GPU可在工作站、
个人计算机、游戏机和移动设备上生成令人叹为观止的互动图形效果。公司在全球拥有
超过8000名员工，总部在加利福尼亚州圣克拉拉。
工作地址：上海研发中心【上海申江路5709号（秋月路26号）矽岸国际2号楼】
二．投递方式
简历发送至HR(Yvette SHEN)邮箱:yvettes@nvidia.com；请注明来源及申请职位
三．职位详情
1.SOC Methodology Engineer
(该岗位招多人，Junior, Senior, Staff, Specialist均可招。薪资范围：20-60W不
等)

SOC methodology team is responsible for researching and implementation for
the methodology and infrastructure used in GPU and Tegra chip design from IP
to SOC, which can help to improve the quality and working efficiency.
Responsibilities:
•    Analyze the existing IP/fullchip environment to create metrics and
identify existing problems.
•    Design and implement the methodology/infrastructure to provide a
friendly framework for chip development.
•    Applied new methodology/infrastructure changes & upgrades,
decommission in different environments.
•    Supported various methodology/infrastructures issues in upgrading
and configuration of technology platforms.
Requirements:
•    BSEE/CS, Master is a plus.
•    At least 3 years working experience on Infrastructure related areas.
Experience on ASIC related area is a strong plus.
•    Strong programing and debugging skills : C/C++, script, Makefile,
etc.
•    Ability to endure stress and meet the challenging requirements of
the field
•     Excellent communication skills and ability to be good at teamwork.
•    Good writing and oral English.

2. Power Methodology Engineer
(该岗位招多人，Junior, Senior, Staff, Specialist均可招。薪资范围：20-60W不
等)

Position title : Senior Power Methodology Engineer
Power methodology team is responsible for researching power expenditures and
workload efficiency to identify architectural, micro-architectural
strategies to improve power efficiency of the next generation GPU and TEGRA
chips.
Responsibilities:
•         Develop the power flow to automate the power expenditures
measurement.
•         Evaluate new low-power technologies and provide feedback to power
ARCH team to improve chip power efficiency on architectural level.
•         Support GPU/TEGRA RTL designers using the power flow to do the
power scrubbing work and improve their power efficiency on micro-arch level.
•         Understand and perform block level and chip-level power analysis.
Requirements:
•         MSEE/MSCS with at least 5 years working experience on ASIC related
areas.
•         Familiar with advanced low power techniques and high speed
clocking desired.
•         Experience in low power ASIC design/verification.
•         Programming languages: Strong Verilog (or VHDL), Perl, Tcl is
must,  C ++ is a plus.
•         Tool Familiarity: PTPX, Synopsys Design Compiler, VCS simulation
tool is must, Power Artist is a plus.
•         Excellent communication skills and ability to be good at teamwork.
•         Excellent  English writing/speaking skills.
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FROM 203.18.50.*