【NVIDIA社招】上海急招芯片低功耗架构分析工程师
一．公司简介
        NVIDIA (英伟达™)(www.nvidia.cn)公司(纳斯达克代码：NVDA)是全球视觉计
算技术的行业领袖及GPU(图形处理器)的发明者。作为高性能处理器的GPU可在工作站、
个人计算机、游戏机和移动设备上生成令人叹为观止的互动图形效果。公司在全球拥有
超过8000名员工，总部在加利福尼亚州圣克拉拉。
工作地址：上海研发中心【上海申江路5709号（秋月路26号）矽岸国际2号楼】
二．投递方式
简历发送至HR(Yvette SHEN)邮箱:yvettes@nvidia.com；请注明来源及申请职位
三．职位详情
Positions summary:
1.    Tegra Power Architect
o    熟悉脚本语言,有低功耗架构相关项目经验优先
2.    Power Analysis Engineer
o    熟悉脚本语言,有低功耗相关项目经验、ASIC 前端设计经验优先
(以上岗位招多人，Junior, Senior, Staff, Specialist均在招。薪资范围：20-60W
不等)

Job Description:
三．职位详情
1.Tegra Power Architect
Job Description:
Power Architect is responsible for the technical direction of Tegra
(Mobile/Automotive) project from power perspective. Interacts with multiple
technologists between developers and project manages to evaluate feasibility
of requirements and determine the priorities for the development.
Responsibilities:
•    Power efficient architecture definition of SOC especially Multi-
Media modules
•    KPI use case power estimation and optimization including future
improvements
•    Optimize perf/Watt of present generation designs and help architect
future projects
•    Guide multi-function design groups during the design cycle to
realize the power targets
•    Design power features and work with a wide set of teams across the
company

Basic Requirements:
•    Solid understanding of high-speed and low-power digital IPs design
•    Familiar with common SOC hardware blocks like memory controller,
multi-media .etc
•    Pre-Silicon multi-media IPs design is a plus
•    Post-Silicon power/perf relative working experience is a plus
•    Able to coordinate low-power feature development cross multiple
function team

2. Power Analysis Engineer
Power methodology/analysis team is responsible for researching power
expenditures and workload efficiency to identify architectural, micro-
architectural strategies to improve power efficiency of the next generation
GPU and TEGRA chips.
Responsibilities:
•         Develop the power flow to automate the power expenditures
measurement.
•         Evaluate new low-power technologies and improve chip power
efficiency on architectural level.
•         Support GPU/TEGRA RTL designers using the power flow and improve
their power efficiency on micro-arch level.
•         Understand and perform block level and chip-level power analysis.

Requirements:
•         MSEE/MSCS with experience on ASIC related areas.
•         Familiar with advanced low power techniques and high speed
clocking desired.
•         Experience in low power ASIC design/verification.
•         Programming languages: Strong Verilog (or VHDL), Strong scripting
languages skills, preferred Perl, TCL/python/C ++ is a plus.
•         Tool Familiarity: VCS simulation tool is must, PTPX, Synopsys
Design Compiler, Power Artist is a plus.
•         Excellent communication skills and ability to be good at teamwork.
•         Excellent English writing/speaking skills.
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FROM 203.18.50.*