Cypress Semiconductor Technology Shanghai （塞普锐思半导体技术上海有限公司)
Job Title: ASIC Design Engineer
Number of Positions: 2
Job Location: Shanghai
Job Type: Full-Time/Regular（全职）
Campus Event:
University Date&Time Venue
TsingHua University 清华大学 7:00PM - 9:00PM, Nov 19th, 2015 二教402室
Job Description:
As a logic designer, will be responsible for IP and full-chip RTL/logic design. He will be involved in all phases of the development, including spec definition, RTL coding, verification closure, synthesis, DFT, STA, etc.
Summary of Duties/Responsibilities:
1. Design Spec Definition: after get marketing requirement, be able to convert it into design spec with feature list, block diagram, input/output definition, and performance analysis, die size estimation, etc.
2. IP design: be able conduct feasibility study, micro-architecture design, and RTL coding
3. Digital IC BE implementation: be able to run synthesis and DFT insertion tool with power aware constraints, need to analysis synthesis log and dft coverage using ATPG tool,
4. Will be involved in STA for timing sign-off,
5. Will work with verification engineer to setup verification plan, and debug for verification closure.
Required Skills
1. Fluent English skills
2. Hard working and team player
3. Takes initiative and sets high goals
4. Smart and confident
5. Self-starter & ability to work in a team environment as an individual contributor
6. Track record of planning and delivering own work completely and on time
Education & Work Experience:
1. Master’s Degree or above in Microelectronics/EE/CE
2. Experience with Verilog logic design is a must
3. Experience with synthesis/sta tool is a must
4. Proficiency in one of script language, such as Perl, Tcl, will be a plus
5. Experience with logic verification will be a plus,
6. Knowledge of ARM CPU, AMBA bus, I2C/SPI/UART interface will be a plus
Please apply this position though below Link:
https://cypress-openhire.silkroad.com/epostings/index.cfm?fuseaction=app.jobInfo&version=1&jobid=2283
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