About US:
NVIDIA (英伟达™)(www.nvidia.cn)公司(纳斯达克代码：NVDA)是全球视觉计算技术的
行业领袖及GPU(图形处理器)的发明者。作为高性能处理器的GPU可在工作站、个人计算
机、游戏机和移动设备上生成令人叹为观止的互动图形效果。公司在全球拥有超过8000
名员工，总部在加利福尼亚州圣克拉拉。
工作地址：上海研发中心【上海申江路5709号（秋月路26号）矽岸国际2号楼】
Contact Info:
简历发送至HR(Yvette SHEN)邮箱:yvettes@nvidia.com; 请注明来源及申请职位
职位咨询：Yvette SHEN: + (86 21) 61043660
Positions Summary:
 上海研发岗
6. ASIC Timing Engineer (Clock)
o ASIC前端/后端背景皆可，熟悉Timing优先
7. Power Analysis Engineer
o 熟悉低功耗优先
8. Power Estimation and Modeling Engineer
o 功耗相关芯片设计经验，优秀的英文沟通能力
9. System software engineer
o 优秀的C/C++编程能力
10. Developer Technology Engineer
o 优秀的C++编程能力，熟悉D3D，有游戏公司从业经验优先
Job Description:
1. ASIC Timing Engineer (Clock)
The NVIDIA Clocks group is looking for an ASIC engineer with
extensive experience in high-speed logic design and timing. The complexity
of clocking structure has grown substantially in order to support high
frequency clock domains. Modern clocking design needs to balance high
frequency clocks with power, DFT, noise, circuit and physical design
constraints.
Responsibilities:
- Perform Synthesis & STA on the designed high speed clock logics.
- Constraint setup and validation in standard & in-house tool flow
- Work in conjunction with Place and Route Engineers to achieve timing
closure
- Develop custom timing scripts using tcl/primetime for clock skew analysis,
special circuits such as clock dividers/switchs, OCC & IO macros interfaces
- Develop scripts for performing ECO's.
- Develop and enhance entire timing flow from frontend (pre-layout) to
backend (post-layout) at both chip and block level.
MINIMUM REQUIREMENTS:
-BS / MS in electrical / computer engineering and related.
-Above 2 years of relevant ASIC experience ideally with a focus in the chip
timing/synthesis/formal closure
-Excellent TCL/Perl scripts skills
-Excellent analytical and problem solving skills
-Fluent English (both written and spoken) and excellent communication skills
-Ability to multiplex many issues, set priorities, and work in a team
environment
-Keep up to date with leading edge technologies
2. Power Analysis Engineer
Power methodology/analysis team is responsible for researching power
expenditures and workload efficiency to identify architectural, micro-
architectural strategies to improve power efficiency of the next generation
GPU and TEGRA chips.
Responsibilities:
• Develop the power flow to automate the power expenditures
measurement.
• Evaluate new low-power technologies and improve chip power
efficiency on architectural level.
• Support GPU/TEGRA RTL designers using the power flow and improve
their power efficiency on micro-arch level.
• Understand and perform block level and chip-level power analysis.
Requirements:
• MSEE/MSCS with experience on ASIC related areas.
• Familiar with advanced low power techniques and high speed
clocking desired.
• Experience in low power ASIC design/verification.
• Programming languages: Strong Verilog (or VHDL), Strong scripting
languages skills, preferred Perl, TCL/python/C ++ is a plus.
• Tool Familiarity: VCS simulation tool is must, PTPX, Synopsys
Design Compiler, Power Artist is a plus.
• Excellent communication skills and ability to be good at teamwork.
• Excellent English writing/speaking skills.
3. Power Estimation and Modeling Engineer
In this role you will be responsible for architecting/developing/correlating
Power Estimation Models/Tools for NVIDIA's GPU/Tegra chips. You will be
interfacing with design teams to understand architecture level features,
create and update power models and power tool features, and help to meet the
organizational needs from management.
RESPONSIBILITIES:
- Architect and develop Power Estimation Models for Dynamic use-case,
Leakage, and IO Power estimation. Design the tools based on these models and
develop solid testing methodology/infrastructures.
- Interface/Coordinate with internal teams and external teams in the US and
India that provides necessary input data to develop the estimation models
and tools.
- Interface with the architecture/management team to discuss requirements,
solutions/methodologies and priorities, including the following:
* Translate higher level feature requests for Power estimation tool to
executable tasks for the team; come up with verification plan and schedule.
* Steer the execution to meet the schedule and do periodic well quality-
assured tool release.
- Correlate/Calibrate these models using measured Silicon data.
- Help study/contribute to Perf/Watt improvement ideas for GPU/Tegra
productions.
MINIMUM REQUIREMENTS:
- MSEE/MSCE, preferably PhD, with specialization/experience related to
Power/Performance estimation techniques.
- Fluent oral and written English to communicate with remote sites like
India, US
- 2+ years of experience of ASIC design. Working experience of any power
estimation techniques, flows and algorithms is a big plus.
- Understands power basics including transistor-level leakage/dynamic
characteristics of VLSI circuits is a plus.
- Familiarity with low power design techniques such as multi VT, Clock
gating, Power gating, and Dynamic Voltage-Frequency Scaling (DVFS) etc. is
desirable.
- Good software programming skills. Python/Perl/C++ preferred. Good skills
with object oriented programming and design.
- Good Understanding of mathematical optimization techniques is desirable.
- Power analysis EDA tools such as PTPX/EPS experience is a plus.
4. System software engineer
RESPONSIBILITIES:
- Self-starting, hands-on system software engineer with good programming
skill and communication skill.
- Design, development and maintenance of SW technologies targeted at
multiple-platforms.
- Resolving reported engineering problems
- Working with other internal teams.
REQUIREMENTS:
- BSEE/MSEE is required.
- 2+ years relevant experience.
- Solid understanding of software development.
- C/C++ expert, as well as scripting languages like Perl or Python.
- Multiple platform programming skills, include at least two of the
following: windows, linux, Mac, IOS, Android, XBOX/PS4.
- Good written and oral communication skills
- Strong debugging and problem solving aptitudes
- Candidate should be comfortable working in a team and have the commitment
to deliver high quality software on schedule
- Good understanding of PC architecture, and system software (Windows
internals and other OS fundamentals)
5. Developer Technology Engineer (游戏图形开发)
Description/
Qualifications: Work with some of the most talented cutting-edge developers
throughout the world. Interact closely with the architecture and driver
teams at NVIDIA in ensuring the best possible experience on current
generation hardware, and on determining trends and features for next
generation architectures. Play with the latest GPU technology to develop new
techniques using GPUs, create technical demos, write whitepapers and present
your work at conferences. Collaborate with developers on 3D rendering
effects and optimizations for specific applications.
MINIMUM REQUIREMENTS:
• Strong knowledge of 3D graphics and GPU technologies, including
shaders, shading languages, and rendering techniques.
• Master in DirectX or OpenGL development.
• Experience in game development or game related products.
• Strong knowledge of C++ and programming techniques a plus.
• Understanding of GPU architectures a plus.
• Good communication skills required.
• Travel for on-site visits with developers and to conferences will be
required.
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FROM 203.18.50.*