Location: Beijing
Contact: wan.seang.ooi@intel.com

Job Description

Your primary responsibility will be working with team to optimize different workloads using tightly coupled FPGA accelerators.
Duties will include:
-Designing and developing Deep Learning code using Verilog,
-Developing and debugging CPU Host SW that effectively offloads parts of workloads to FPGA,
-System debug & Validation of FPGA prototype systems,
-Performance analysis and tuning of workloads on heterogeneous platform,
-Developing OS and device drivers

Job Requirement
-1 or more years' experience with implementing algorithms on FPGAs.
-Experience in programming in C and/or C++ and assembly language.
-Experience in design, development and debugging of multithreaded programming code.
-Experience in hardware development using Verilog or System Verilog (or VHDL).
-Familiarity with FPGA design tools.
-Knowledge of deep learning technologies (Alexnet, Caffe, etc.)
-Very good Linux OS understanding and experience in software development for Linux.
-Good English communication skills, both written and oral.
-Disciplined design approach, and ability to work smoothly with a team.
Additional qualifications and experience that would be useful:
-Knowledge of CPU architecture, general GPU architecture.
-Prior experience working with heterogeneous (FPGA, CPU, GPGPU) hardware systems.
-Subject matter expertise in a particular class of algorithms, e.g. speech, image processing, etc.

Please subject your email as ‘Graduate Intern Technical_Beijing_XX days per week_XX months’ when applying to wan.seang.ooi@intel.com.
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