If you have interest, feel free to send your resume to vicky.cai@amd.com/nina.zhang@amd.com

Location: Beijing

Job Responsibilities:
o Mainly target is to work on below key areas for Power team:
o Power reduction Methodology in Digital physical design
o Floorplan, Place and Route , Timing/DRC/IR/EM checking/fixing
o flows/tools methodology

Requirement:
o Understanding basic ASIC design flow
o Tier 1 or 2 University, institute
o Master student in microelectronics, or related area
o With experience on Verilog or System Verilog
o Sufficient knowledge in Perl/Python/Ruby/Java/C/C++ is a strong plus
o Nice to have development experience under Linux, knowledge of Shell/Make/VIM/…
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FROM 58.247.170.*