【职位名称】Logic Verification Engineer

【部门】CPU-Platform

【简历接收信箱】hrbj_6@viatech.com.cn
投递简历的邮件请注明“应聘+Logic Verification Engineer（logic3）+水木”

【Responsibilities】
USBHUB verification; USB host model.

【Requirements】
1. M.S/B.S in Computer Science or Electrical Engineering or Microelectronics;
2. Be familiar with Verilog ;( must)
3.Graduate students who will graduate in 2010 are preferred;
4. Available for at least six months and four days a week.
5.了解USB Protocol优先考虑;
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FROM 203.86.66.*