爱立信招聘FPGA Design/Verification Engineer Intern
Working Location:Beijing
Responsibilities:
Job Objective:
To be responsible to perform functional verification of FPGA product

Responsibilities:
-          Be responsible FPGA/CPLD Design and Verification for CDMA products;
-          Make test plan and design simulation environment for RTL design
-          Derive test cases from design features, implement test cases, verification debug and on board debug.
-          Develop and implement scripts for Simulation regression running on Windows/Linux platform
-          Run regression and track test results.

Qualification & Competence requirements:
Qualifications & Requirements:
-          Majored in EE of Master degree.
-          Have knowledge/experience on logic design verification, verification methodology of OVM is a plus
-          Familiar with Logic design language of Verilog and SystemVerilog, VHDL is a plus
-          Telecommunication (data, wireless) knowledge and project experience is a plus
-          Experience in testbench coding and functional verification work, experience on OVM is preferred!
-          Working on Linux OS is a plus.
-          Serious-minded in work,
-          Good at MS Office
-          On site work for at least 4 days a week and can garantee the internship throughout 2011.


邮箱：recruitment.etc@ericsson.com

邮件题目请注明： BJ15 FPGA Design & Verification intern + 姓名+学校名称+每周可以实习的天数
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