【 以下文字转载自 METech 讨论区 】
发信人: googl (爱猫猫爱老婆), 信区: METech
标  题: LSI招intern
发信站: 水木社区 (Mon Apr 11 11:46:21 2011), 站内

JD在下面，各位在校的同学们如果有兴趣可以试试，Verification, desin, analog都有，最好能工作半年以上吧，如果表现很好，会考虑直接校园招聘招进来，做的东西都算比较有挑战性吧，对个人的成长我觉得是会有很大帮助的，希望大家踊跃推荐啊，地点在上海，待遇嘛我可以说应该是相当好的，有兴趣的可以站内或者发邮箱到stanlyliusu@gmail.com.
JD:
Job Description
-Working with an Architecture/Algorithm Development Team to finalize system architecture for optimal implementation of digital signal processing algorithms, including architectural definition and tradeoffs, die size estimation.
- Digital logic design, Verilog coding, logic synthesis, both RTL and gate level verification, formal verification and static timing analysis.
- Perform some transistor level high speed digital integrated circuit design various cells and blocks within custom chips for the hard disk drive industry. Examples of cells and blocks include multiplexors, adders, multipliers, dividers, specific functional macro blocks,
- Work very closely with physical design engineers from floorplan through final parasitic extraction to ensure smallest area and highest performance possible.
LSI Corporation is a leading provider of innovative silicon, systems and software technologies that enable products which seamlessly bring people, information and digital content together. We offer a broad portfolio of capabilities and services including custom and standard product ICs, adapters, systems and software that are trusted by the world's best known brands to power leading solutions in the storage and networking markets.
We value the diversity of our people. LSI is an Equal Opportunity Employer.
Specific Knowledge/Experience
-Communicate effectively within a global business environment (must be proficient in both spoken and written English).
- Experience in logic design, synthesis, static timing analysis, and verification.
- Experience with ASIC EDA tools used in synthesis, simulation, static timing analysis, and formal verification.
- Experience in developing simulation and verification test benches.
- Knowledge of Verilog/VHDL design languages.
- Excellent technical troubleshooting and demonstrated problem solving skills.
- Must be willing to follow a structured design approach including design for reuse and provide thorough design documentation.
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FROM 218.1.16.*