对象:上海高校研一/研二/大三学生，能实习半年以上，每周不少于3天。
有ASIC或FPGA经验的童鞋请踊跃投递简历吧！
简历请发送到monlin@nvidia.com.

DFT Engineer Intern

Location: Shanghai, China

Please send resume to monlin@nvidia.com

RESPONSIBILITIES:
Responsible for DFT feature and VerifPlan setup
DFT area work include Jtag ,SCAN, Boundary SCAN, MBIST and Analog
Develop test DFT cases and procedure
Responsible to use and maintain dft and verification flow
Generate test vectors and post silicon validation

REQUIREMENTS:
-BSEE, MSEE is preferred
-strong logic design and verification back ground
- possess knowledge of DFT (scan insertion, Mbist, JTAG and etc.)
- Skilled in Perl/tcl, programming
- Working knowledge in C/C++, makefile is a plus
- Prefer to have experience in logic simulators and debug tools (vcs, ncsim, v
erdi and etc.)
- Prefer in verilog HDL
- Problem solving and analytical skills

Please send resume to monlin@nvidia.com
--
FROM 203.18.50.*