DFT Project Leader@上海 简历发 ic@hi-talent.com 微信xindejane
Responsibility
As a DFT project leader, you should be work as a chip or sub-chip DFT leader for high performance ASIC design. Understand frond-end and back-end design requirement and limitation. Support Customer on advance DFT feature requirement. Specify the project DFT Design spec. Help Block level DFT engineer to resolve key design problem. Develop and maintain project DFT flow.
Requirement:
5 years+ DFT experiences and 2 year + top level DFT project experience.
Deep understanding on DFT Design for large scale and high performanceSOC chip design.
Strong knowledge on STA and Test timing closure.
2+ TapeoutATE bring-up and diagnose experience
Massive product ASIC design experience.
Solid Background on Verilog and SOC design
Familiar with SNPS and Mentor DFT tools
Familiar with PT or Tempus STA tools
Familiar with simulation and ATE debug
Good at makefile, tclandperl scripts
DFT Flow Develop Engineer@上海 简历发 ic@HI-talent.com 我微信xindejane
Responsibility
As a Flow develop engineer you will work with Global DFT flow development team, to develop and maintain DFT/Synthesis/STA flow to support multi large scale high performance SOC design. You should familiar with various related EDA tools, and verify and integrated them into makefile base system. You should work as a technology leader of DFT feature development and improvement. Help project engineer to resolve key design problem.
Requirement:
3+ years DFT design experiences
Solid Background on Verilog and SOC design
Strong knowledge on DFT design, like SCAN, MBIST, IP test.
Strong skill on SNPS and Mentor DFT and simulation tools
Familiar with SNPS and cadence STA/Synthesis/PnR tool
Familiar makefile, tcl and perl scripts
Familiar with version control system setup and maintain, like github or svn.
STA静态时序分析@上海 简历发 ic@hi-talent.com 微信xindejane
1. 负责SoC芯片前端流程，包括综合，形式验证, DFT测试方案制定以及静态时序分析等
2. 负责 Module 和 SoC 层次的 DFT 实现，包括 Scan、Boundary Scan、MBIST 以及 IP test 等
3. 负责 Module 和 SoC 层次的 timing constraints， UPF file， Synthesis，STA和formal验证
4. 负责SoC低功耗流程
5. 与后端工程师合作进行时序收敛工作
6. 与前端设计工程师合作解决timing问题
7. 负责 ATE 测试中的向量产生和 debug
岗位要求：
1. 本科及以上学历，通信、微电子相关专业，熟悉ASIC设计
2. 3年以上STA/synthesis/formal/DFT 工作经验，熟悉低功耗设计流程
3. 熟练使用Synopsys或Cadence工具如DC/PC/Formality/Teramax, Genus/Encounter等， 熟练使用Mentor等DFT工具如TestKompress/FastScan等。
4. 能够熟练使用 Perl、Tcl 和 Shell 脚本编程
5. 熟悉AMBA总线、SOC结构者优先
6. 具有良好的表达沟通能力及团队合作精神，具有很强的独立工作能力及动手能力
后端设计@上海 简历发 hr@hi-talent.com
岗位职责：
1、根据公司的项目计划，按时完成netlist in到gds out的APR各项设计工作：
包括完成相应的floorplan，与系统封装同事及前端同事充分沟通并给出pin assignment调整建议，
时序收敛，功耗分析及优化以及IP merge，确保项目顺利tapeout。
2、按照SOC物理实现APR流程的开发规范和标准，进行模块级或芯片级APR设计工作。
3、完成tapeout流程：in-house 及第三方IP merge，physical verification包括DRC&LVS&Antenna check，协助完成MT-form填写，确保芯片顺利tapeout。
4、负责芯片流片后的ECO评估及物理实现APR工作。
5、根据行业发展趋势及技术水平，协助有关部门制定开发规划及设计流程，重点在对EDA工具的评估与掌握。
任职资格：
1、本科以上学历，5年以上工作经验，参与2个以上芯片产品研发APR相关工作经验
2、具备扎实的SOC设计与物理实现基础知识，熟悉SOC APR设计开发流程，熟悉掌握版图及物理验证的知识，
熟悉Cshell, tcl, perl等语言，熟练使用相关工具。
Best Regards
Jane.Jin
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
上海芯得企业管理咨询有限公司
上海芯相会企业管理咨询有限公司
Mob: 18502155252
E-Mail: Jane-Jin@hi-talent.com
微信： xinde_jane
QQ: 1600548210
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http://weibo.com/u/1716864892webside： www.hi-talent.cn
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