再借贵版广告一下我们团队的人员需求，地点北京，南京，杭州，上海，成都，西安，苏州：
主要是PLL,ADC/DAC,SERDES 方向的模拟以及数字设计工程师，感兴趣联系我，13910278038，微信同号。
  
1.Job summary (Analog/Mixed-signal design engineer – senior to staff level)
  
oProvide important contributions to the product for high performance ADC and DAC products.
oDesign key modules and integrate top-level schematic.
oCollaborate with the digital designers for mix-sig designs
oGuide layout engineers.
oParticipate in product definition, process selection, lab verification, and release to production.
oFollow up the whole product development process from product definition to release.
oGrow with the team and company in technical, managerial, and financial aspects.
  
Basic Qualifications:
oPassion and knowledge about mixed signal design, especially the OpAmp, Switched-cap, DAC and ADC product design.
oBe familiar with mixed-signal ICs design, methodology, and process.
oHave deep knowledge of silicon physics, silicon processes and IC packaging technologies.  
oMust have experience with mixed-signal design tools such as Cadence Spectre and AMS.
oPossess good understanding of thermals, mechanical and packaging challenges. Possess knowledge of high-volume manufacturing technologies and production variance.
oBe able to model both modules and top level with verilogAMS and/or other languages.
oExperience with I/O and ESD is a plus.
oExperience in lab to test the product.
oHave good communication skill
oHave good English reading and writing capability
  
Education
  MSEE with 3+ years’ experience
  
2.Job summary (Digital IC Design Engineer, Senior and Staff)
  
Responsibilities
oResponsible for defining and developing digital PLL architecture based on product spec.
oResponsible for digital design including RTL coding, verification/simulation, synthesis, static timing analysis, scan insertion and test pattern generation
oOverseeing automatic place and route
oValidating/debugging of silicon
  
Requirements
oBachelors with 5+ years, or masters with 3+ years of experience in digital and mixed signal IC design.
oExperience of mix-signal IC design with an emphasis on digital flow.
oExperience in behavioral models of analog circuits and mixed mode simulation.
oExperience in PLL design is a plus.
oExperience in silicon validation in the lab with spectrum analyzers, oscilloscopes, signal generators, and etc
oFamiliarity with the design and use of IP blocks like SPI, I2C, I3C, SMBus, EEPROM, and OTP.
oExperience with Cadence and/or Synopsys design tools
oExperience with verilog-HDL, SystemVerilog, UVM
oFamiliarity with Perl, TCL, Python and/or C++ scripting
oExperience in system level modeling and analysis with C/Matlab/MathCad is a plus
oExperience with design prototyping and validation in FPGA is a plus
oGood writing and communication skills
oBe innovative
Keywords
Digital and mixed signal IC design, PLL design, high speed design
  
3.Job summary (Analog/Mixed-signal design engineer – senior to staff level)
  
Your responsibilities, as a member of timing product development team, include:
oProvide important contributions to the timing product for high performance networking, communication and data center products.
oFollow up the whole product development process from product definition to release.
oDesign key modules and integrate top-level schematic.
oParticipate in product definition, process selection, lab verification, and release to production.
oGuide layout engineers.
oGrow with the team and company in technical, managerial and financial aspects.
  
Basic Qualifications:
oPassion and knowledge about mixed signal design, especially PLL and other timing product design.
oMust be familiar with mixed-signal ICs design, methodology and process.
oMust understand RF transistor modeling and circuit noise theory. Have solid understanding of phase noise and jitter.
oMust have deep knowledge of silicon physics, silicon processes and IC packaging technologies.  
oMust possess good understanding of thermals, mechanical and packaging challenges. Must possess knowledge of high-volume manufacturing technologies and production variance.
oMust have experience with mixed-signal design tools such as Cadence Spectre and AMS.
oMust be able to model both modules and top level with verilogAMS and/or other languages.
oExperience with high speed I/O and ESD is a plus.
oExperience with <=65nm CMOS technologies is a plus.
oExperience with delta-sigma modulator theory is a plus
  
Education
oMSEE with 3+ years’ experience.
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