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以下是多家公司(大厂为主）的职位，成都有soc设计、cpu设计、soc验证、DFT、后端、模拟等职位




DFT设计专家/高级专家-成都
岗位描述
The candidate is expected to be responsible for following tasks:
- Participate in complex Chip DFT/DFD feature and architecture definition
- Implement DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic
- Generate DFT related timing constraints and work for timing closure
- Develop and verify high coverage and cost effective test patterns for the production test
- Design, implement and verify other DFX (debug, characterization, yield etc) feature
- Evaluate and establish the advanced DFT/DFD tools and flow
岗位要求
6+ years for Bachelor or 3+ years for master degree experience in DFT design and verification, test pattern development

KEY KNOWLEDGE, SKILLS AND ABBILITIES REQUIRED
- Good Knowledge of Scan/ATPG, MBIST and boundary scan and other DFT techniques
- Good Knowledge of industry DFT tools like DFTMax, TetraMax ,TestKompress, FastScan, Tessent Mbist, SMS etc
- Good knowledge of digital SoC/ASIC design, including STA, verification and RTL coding
- Proficient in hardware description languages such as Verilog, System Verilog and VHDL
- Good Knowledge of script language, such as Tcl, Python, Perl
- Good English hearing, speaking, reading and writing capabilities
- Strong commitment to schedule and work quality, good team playe



资深后端专家
岗位描述
As a member of the PD team, you will build the next generation networking SoC in advanced process. You will drive the backend flow through the entire RTL2GDS process including floor planning, P&R, timing, PI, and sign-offs. You will also conduct PPA optimization.

You responsibilities include, but not limited to:
* Build backend flow on state-of-the-art processing node
* Create SPECs for PD sign-off
* Work closely with architecture and design team to optimize PPA
* Floor planning, design synthesis, equivalence checks, partitioning, IO assignment and IP integration, CTS and power grid, P&R , timing closure, power analysis etc.
* Design and timing ECOs and sign-offs
岗位要求
BS or MS of EE, 5+ years of experience with the whole RTL2GDS process
* Understanding the state-of-the-art of processing node, custom lib and optimizations
* State-of-the-art experience with CTS and power grid planning, power integrity is a plus
* Experience with relatively large designs (>10m flops) on advanced process nodes and optimization methodology toward top performance and low power
* Understanding of DVFS, DFT, DFY, DFM is a plus

Some hands on with following tools are needed:
* Floor planning and P&R: Cadence Innovus and/or Synopsys ICC2
* Synthesis: Synopsys DC/DCG
* Formal Verification : Synopsys Formality and/or Cadence LEC
* STA: Primetime-DMSA
* PI : Apache Redhawk
* Physical Design Verification: Synopsys ICV, Mentor Calibre
* Scripting: TCL/Perl is required, Python is a plus



模拟电路工程师
工作职责：
1.独立完成系统架构设计、分解各子模块的设计指标和接口定义；
2.根据产品设计指标完成电路设计开发、验证；完成设计文档，确定测试方案；
3.指导版图工程师完成符合电路设计要求的版图设计；
4.配合应用工程师，设计模拟相关的外围应用电路；
5.配合应用工程师，进行设计的测试，调试和验证，并支持解决应用中模拟相关问题；

任职资格：
1.电子信息科学与技术、微电子等相关专业本科及以上学历；
2.至少三年以上模拟电路设计经验，熟练掌握OPA、VBG、AD、DA、PLL等基本电路，有MIPI,ETHERNET等接口设计经验优先；
3.能熟练使用EDA具进行电路级和行为级的仿真分析；
4.能使用各种仪器设备进行芯片的测试评估和DEBUG的工作；
5.具有基本英语听、说、写能力，较强的学习能力和团队协作精神。
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