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手上有数十家IC设计公司的职位,包括架构、数字设计、验证、数字综合/实现、DFT、后端、模拟设计、软件等等，地点包括一二线城市


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上海招聘数字设计专家/Leader（serdes/DDR/ USB  /MIPI / PCIE/UFS /安全等任一方向都可以）

leader/manager ：需要硕士八年以上   该领域深耕多年  技术扎实（可以没有管理经验）
岗位70%工作以上技术

具体信息，欢迎问询
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SOC-System IP Design Engineer
工作职责
1.负责世界顶级芯片的研发和设计工作
2.和相关部门紧密合作，完成从产品定义，架构定义，逻辑设计，物理设计，验证，流片和量产的全流程
3.完成IP模块， 子系统和SOC层的设计，集成。

工作要求
1. 熟悉Synopsys或者Cadence 或者其它EDA工具, 如Spyglass, Linting, CDC，DC (Design Compilier), PT (PrimeTime),
2. 熟悉SoC芯片流程设计 (IC design flow)
3.熟悉Verilog/SystemVerilog；
4. 熟悉模块级结构设计（IC design, microarchitecture），RTL实现和相关验证工作 (simulation, verification, emulation)
5.熟悉ARM架构和ARM IPs, AXI, AHB, Cache, SMMU, Coresight等
6. 熟悉SoC集成，总线架构设计BUS/NOC，
7. 熟悉高速接口设计， 包括： DDR， PCIE， USB， CSI， DSI， Serdes， C-PHY, D-PHY
8. 熟悉安全芯片模块, 加解密（crypto engine）
9. 熟悉视频图像处理ISP

PCIE设计高级/资深专家-上海 深圳 P8
岗位描述
1. 与市场/架构团队合作，根据业务需求，完成PCIe IP 架构和特性的定义；
2. 领导设计团队完成自主PCIe IP的开发；
3. 管理和跟踪团队开发和交付，保证交付质量；
4. 负责芯片回片之后的相关调试工作。
1. Work with Market/Architect team, work out PCIe IP micro architecture and feature definition；
2. Lead design team for in house PCIe IP development；
3. Manage the project, take responsibility of delivery and guarantee the quality；
4. Take responsibility of chip bring up work。
岗位要求
相关专业研究生学历，至少8年以上相关经验, 3年以上项目和团队管理经验。并满足以下方向
1. 熟悉芯片设计流程，并有多次流片的经验和芯片回片的调试工作，先进工艺相关经验者优先。
2. 熟悉PCIe协议和架构，并拥有自主设计相关经验，了解PCIe底层软件和驱动架构者优先。
3. 熟悉大规模SOC，处理器体系结构，熟悉主要总线协议, 以及常用数字 IP, 参与过大型芯片顶层整合者优先。
4. 问题解决能力强而且全面, 具被优秀团队沟通协作能力。

Master in EE/CS, 8+ industry experience, 3+ project and people management, with skills in
1. Familar with IC design flow/methodology, mutiple tapeout in advanced technology, has experience and ability of chip bring up.
2. Familar with PCIe architecture, has experience of in house IP design, Knowledge with PCIe firmware of drivers
3. Familar with large scale SOC, processor, On chip bus/fabric and common IPs.
4. Strong problem solving abilities. Great communication and collaboration skills to interact with other team members.



SOC Design Engineer -- PCIE
Location: Beijing/Shanghai/Wuhan
Job Description:
As part of the ASIC design team, engineer will mainly focus on following areas, but not limited to:

1.Deeply understand system level requirements and IP features, create sub-system design.
2.Prepare micro-architecture spec and verification plan for IP, subsystem and chip top
3.Assist with chip bring up and perform silicon functional/performance validation.
4.Assist with implementation team on netlist release, P&R suggestion and timing tuning.

Job Requirements:
1. Degree in electrical engineering, computer engineering or related technical fields
2. Good knowledge of Verilog/SystemVerilog.
3. Hand on experience on any of these tasks: Lint/CDC check, SDC/UPF generation, Synthesis, Formal
4. A high-level of self-motivation and a proactive approach to solving problems

Solid knowledge in one of the following areas is a plus:
1.Hands on experience on PCIE Subsystem design and netlist develivery;
2.Familiar with Vendor’s PCIE controller and Phy, both function and test mode.
3.Familiar with AMBA spec and SOC architecture.
3. Familiar with frontend ASIC design methodology/flow.
4. Experience of Low power design ；



DDR设计高级/资深专家-上海 深圳
岗位描述
1. 与市场/架构/SOC团队合作，根据业务需求，完成DDR IP 架构和特性的定义。
2. 领导设计团队完成自主DDR IP的开发。
3. 管理团队开发和交付，达到PPA指标，保证交付质量。
4. 承担芯片回片DDR bring up相关工作

1. Work with Market/Architect team, work out DDR IP micro architecture and feature definition
2. Lead design team for in house DDR IP development
3. Manage the project, take responsibility of delivery， meet PPA metric and guarantee the quality
4. Take responsibility of chip bringup.
岗位要求
相关专业研究生学历，至少8年以上相关经验, 3年以上项目和团队管理经验。并满足以下方向
1. 熟悉芯片设计流程，并有多次流片的经验和芯片回片的调试工作，先进工艺相关经验者优先。
2. 熟悉JEDEC协议，具备DDR/HBM/GDDR/LPDDR等相关经验，拥有自主开发DDR控制器的经验，能根据不同业务需求，完成控制器的性能优化。
3. 熟悉大规模SOC，处理器体系结构，熟悉主要总线协议, 以及常用数字 IP, 参与过大型芯片顶层整合者优先。
4. 问题解决能力强而且全面, 具被优秀团队沟通协作能力。

Master in EE/CS, 8+ industry experience, 3+ project and people management, with skills in
1. Familar with IC design flow/methodology, mutiple tapeout in advanced technology, has experience and ability of chip bring up.
2. Familar with JEDEC protocol, worked on DDR/HBM/GDDR/LPDDR project, has experience of in house IP design and ability for performance optimization based on diffrent busness model
3. Familar with large scale SOC, processor, On chip bus/fabric and common IPs.
4. Strong problem solving abilities. Great communication and collaboration skills to interact with other team members.
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