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手上有不同类型的数十家IC设计公司的职位   包括不限于数字设计  验证  模拟设计  综合 后端等   地点包括一二线城市


以下是合肥部分数字验证。数字设计。模拟设计职位，欢迎问询（需要直接经验，暂无实习岗位）


数字验证工程师
Responsibilities:
1. Creating test plan according to design spec
2. Designing and developing verification environment;
3. Debugging SoC regression fAIlure
4. Creating system checker/monitors and system UVCs, code & function coverage in SOC
5. Creating C test case running on arm in SOC
6. Creating UVM test case in SOC
Qualifications:
1. Education and Experience-Bachelor or above with 3 years of work experience
2. Skills and Knowledge-
verilog
System Verilo
UVM
Perl/Python/Tcl
AXI/AHB/APB
Co-sim between hardware and software is an additional plus
C/C++ is an additional plus
USB/Ethernet/PCIE/SATA/SPI/I2C/etc.
experience is an additional plus
ARM related experience is an additional plus


二、
SOC Staff/Senior Design Engineer

Job Description：
Understanding the digital designs(Chip & IP);
Designing chip Arch(Including Bus, Clock, IO_MUX, Power Domain, etc);
Writing SDC and UPF;
Running RTL and gate level simulation and regression;
Coworking with Verification team, BE team and FPGA team;

Job Qualification：
Minmum of 5 years digital design experience;
Familiar with design languages(verilog, System Verilog, SVA etc.);
Familiar with Simulation & Debug Tools(VCS, Verdi, etc.);
Familiar with Synthesis Tools(DC or RC.);
Familiar with asic Design Flow;
Scripting skills (perl, tcl, makefile, Python etc.) is a plus;
Knowledge in low power design is a plus;
Knowledge in STA is a plus;

三、
SoC，Sr. Verification Engineer
Shanghai
Suzhou
1.understanding the digital designs(Chip & IP);
2.Developing verification and regression plans;
3.Designing and developing verification environment;
4.Running RTL and gate level simulation/regression;
5.Coworking with Design&FPGA team;
6.Code/functional coverage development, analysis and closure;
1.Minmum of 5 years verification experience;
2.Knowledge in asic design process and verification tools/env (UVM);
3.Familiar with design and verification languages(verilog, System Verilog, SVA etc.);
4.Familiar with Simulation & Debug Tools(VCS, Verdi, etc.);
5.Familiar with ASIC Design Flow;
6.Scripting skills (perl, tcl, makefile, Python etc.) is a plus;
7.Experience in SOC chip level verification, including test plan and testbench development, test case development;
8.Additional qualifications include: 9.Good IC verification skills and basic knowledge of logic or circuit desing, good communication and problem solving skills;




四、
IC设计工程师
职责描述 ：
1、实现系统要求分析,对设计进行模块分割、接口定义；
2、负责算法映射与芯片架构探索；
3、 RTL设计实现；基于面积、时序要求的优化设计；设计报告编写。
4、基于验证结果，分析排错；
5、负责相关文档、报告的撰写、归档。
经验技能及其他要求：
1、熟练操作计算机、前端EDA工具；
2、熟悉微处理器体系结构，熟悉面向硬件架构的算法映射，熟练掌握面向实现的RTL级设计；
3、熟练掌握数字电路设计、数字电路综合技术；
4、能够针对RTL/netlist进行时序、功耗、面积和电路性能的优化；
5、熟练掌握verilog/Vhdl等硬件描述语言，善于学习；
6、熟悉PCIE、SATA、DDR等，熟悉AXI/APB/AHB等总线协议。
7、需要相关工作经验5年以上。



五、IC验证工程师
职责描述 ：
1，负责数字IP和SOC产品的验证；
2，制定验证规格和测试计划，并搭建基于UVM的验证平台；
3，执行验证计划，编写测试用例，开展递归测试，完成问题的调试和修复，并完成覆盖率的收集和分析；
5，FPGA以及EMULATOR调试验证；
6，为芯片回片测试提供支持,5
经验技能及其他要求：
1，熟悉PCIE和SERDES，熟悉AXI/APB/AHB等总线协议；
2，熟悉常见dsp、cpu架构；
3，熟悉System Verilog和UVM验证方法学；
4，熟悉FPGA开发；


六、Sr. Digital Design
Responsibilities:
?Work on the development of world advanced wireless charge or PMIC project
?Perform digital circuit designs including architecture, RTL coding, simulation, verification, synthesis, and layout support
?Perform test, evaluation and debugging of prototype ICs
?Design for test, design for quality, design for mass production
?Assist with top level mixed-mode simulations

Requirements:
?M.S. in electrical engineering or a related field; at least three years of significant hands-on technical experience in Verilog
?Strong experience in digital design implementation including architecture, logic and physical synthesis with constraints, timing analysis, gate level simulations
?Experience with Industry standard design tools for RTL synthesis and timing analysis
?Experience with embedded MCU, NVM, and RAM in advanced technologies
?Strong interpersonal and communication skills
?Experience with UVM is a plus
?Experience with P&R is a plus
?Experience in design prototyping, emulation and validation using FPGAs is a plus

七、
职责描述:
1.根据需求和设计文档，制定验证计划，搭建验证环境，编写测试用例。
2.分析功能/代码覆盖率，识别覆盖率漏洞，管理和控制验证风险，进行流程优化。
3.参与验证策略的研究，以提高自动化和生产力，包括不仅限于自动化flow、度量指标建立、验证架构和方法探索。
4.指导和培训初级验证工程师。

任职资格：
1. 3年以上(MS)或5年以上(BS)工作经验。
2.熟悉先进的验证方法(UVM、VMM、OVM等)、工具和流程。
3.熟悉HDMI/DDR/USB/ETHERNET IP者优先。
4.有视频、音频经验者优先。
5.精通任一脚本编程语言:perl、shell、ruby、python等优先。
6.流利的英语听说读写能力优先。

八、数字验证工程师
Job Responsibilities:
·能够建立UVM验证环境搭平台并能够进行模块和系统级验证，根据需要集成第三方验证IP和C model
·经过验证的ASIC / FPGA验证能力和测试平台开发经验
·了解System Verilog（SV）和面向对象的编程概念
·使用UVM / OVM方法开发模块级和子系统级测试台的经验

Requirements:
·5年以上数字验证经验
·熟练使用C语言
·对UVM/VMM、SystemVerilog 熟练使用
·熟悉SOC设计一般架构
·有RISCV验证经验的优先

九、资深模拟芯片设计工程师 上海 合肥
职位详情
Performance Objectives
1.Definition, modeling, design, and verification of highly integrated power-management ICs such as DCDC converters, LED drivers, linear regulators, and other types of Analog/mixed-signal ASICs.
2.Ability to work at any level of the design is absolutely essential.
3.Implement full-featured behavioral models of complex analog/mixed-signal ICs.
4.Interface with test, product, and applications engineering to drive the design to a successful production release.
5.Provide technical leadership including mentoring less senior members of design team, contract design resources, and layout supervision.
6.Assist in silicon validation and lead troubleshooting efforts to root out unintended circuit behavior through simulation, FIB, and intensive laboratory debugging.
7.Close collaboration with product definition and system architecture groups.
Requirements
1.BS with 5+ years or MS/PhD with 3+ years of analog mixed-signal design experience preferably in the power-management application area.
2.5+ years of analog, mixed-signal IC design experience encompassing diverse areas such as: DC-DC conversion: switch-mode or linear regulators ADC/DAC PLL/CDR Continuous and discrete-time analog integrated filters I/O interfaces Analog test (DFT) interfaces
3.Proven track record of technical leadership including multiple products taken from specification through design, release, volume manufacturing, and field support.
4.Detailed knowledge of power conversion architectures and analytical methods highly desirable.
5.System modeling skills in SIMPLIS or Matlab highly desirable.
6.CAD tools: Must be familiar with Cadence virtuoso CAD tool suite: schematic, layout, simulation and verification. Must be experienced with top-down analog behavioral modeling methodology including fluent use of Verilog-A/AMS as appropriate. Skill in design automation tools and scripting environments is essential. Familiarity with Verilog and digital design and verification is a plus.
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FROM 219.140.141.*