JD仅作参考，有相关经验和背景既可，有意者联系liang.jia@nxp.com, 谢谢！
NXP Semiconductors N.V. (NASDAQ: NXPI) enables secure connections for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has approximately 29,000 employees in more than 30 countries and posted revenue of $8.61 billion in 2020.
Title： Principal Digital IP Design Engineer
Location：Suzhou
Responsibilities
o Develop RTL for digital IPs or subsystems based on architectural requirements
o Build testbench, create tests to verify digital IPs, and then report coverage of verification
o Develop functional timing constraints for IPs
o Run IP check flows of Lint, CDC/RDC, DFT, Synthesis, etc.
Requirements
o 10+ years of work experience in RTL Design and Verification
o Master’s degree in Microelectronics, Electronics, Electrical Engineering, Computer Science or relevant disciplines
o Mandatory Tool Exposure: NCSim/VCS, Spyglass or Questa LINT/CDC
o Mandatory Skills: Verilog/SystemVerilog
o Knowledge on USB or multimedia(display, graphic, video) preferred.
Title： Senior Digital IP Design Engineer
Location：Suzhou
Responsibilities
o Develop RTL for digital IPs or subsystems based on architectural requirements
o Build testbench, create tests to verify digital IPs, and then report coverage of verification
o Develop functional timing constraints for IPs
o Run IP check flows of Lint, CDC/RDC, DFT, Synthesis, etc.
Requirements
o 4+ years of work experience in RTL Design and Verification
o Master’s degree in Microelectronics, Electronics, Electrical Engineering, Computer Science or relevant disciplines
o Mandatory Tool Exposure: NCSim/VCS, Spyglass or Questa LINT/CDC
o Mandatory Skills: Verilog/SystemVerilog
o Automation Tools: Shell, TCL, Perl, Python, etc.
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