ob Title
IP AE: PCIe, DDR, Ethernet and SERDES IP
EDA AE: Synthesis, PR and STA
IP Design: Digital Design, Design Verification
R&D: C/C++,data structures, Algorithm
Others: DFT, FPGA, Analog, layout
Location:
Shanghai/Beijing/Wuhan/ShenZhen
Contact
内推方式是员工上传简历
51633508 (可加微信，备注内推)


下面是武汉的校招岗位
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FROM 115.47.202.*