代码是这样：
always @(posedge clk or negedge rst_n)
if (!rst_n)
    data_out <= 32'd0;
else
    data_out <= data_in;

激励1：
initial begin
...
#20
@(posedge clk)
data_in = 32'h12345678;
...

end


激励2：

always @(posedge clk or negedge rst_n)
    if(!rst_n)    data_in <= 32'd0;
    else     data_in <= data_in + 32'h12345678;


激励1是data_in和data_out是同步的，激励2中data_out要慢data_in一拍。
激励1为什么是这样？竟然同步！
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