[合集] 请教大家一个问题(0)

2008-04-18 zhaoguangjie|2008-04-18 zhaoguangjie

[合集] "Critical Warning: Timing requirements were not met.(0)

2008-04-18 zhaoguangjie|2008-04-18 zhaoguangjie

[合集] FPGA怪问题(0)

2008-04-18 zhaoguangjie|2008-04-18 zhaoguangjie

[合集] 对SRAM先写后读的操作(0)

2008-04-18 zhaoguangjie|2008-04-18 zhaoguangjie

[合集] 关于testbench(0)

2008-04-18 zhaoguangjie|2008-04-18 zhaoguangjie

[合集] 升余弦滚降滤波器和低通滤波器有什么区别啊？谢谢各位高(0)

2008-04-18 zhaoguangjie|2008-04-18 zhaoguangjie

[合集] 用什么软件画时序图比较方便？(0)

2008-04-18 zhaoguangjie|2008-04-18 zhaoguangjie

关于FPGA用VHDL赋初值的问题(9)

2008-04-15 Makefile|2008-04-18 frankrick

vhdl中std_logic_vector和real变量相互赋值的问题(1)

2008-04-15 reset|2008-04-17 reset

fpga设计中，怎么造延迟？(11)

2008-04-14 rmflyer|2008-04-17 pizzafool

发一个时钟和时序分析的资料(0)

2008-04-16 mabenli|2008-04-16 mabenli

ise中怎么查看vhdl程序中间变量？(4)

2008-04-15 prioper|2008-04-15 prioper

Synplify 啥版本比较好用哇？(1)

2008-04-13 heartfield|2008-04-15 BlackBlues

请问xilinx的v4的LUT延时有多大？(2)

2008-04-14 sandyhan|2008-04-14 darui

谁能解释一下LUT4这个primitive前面的attribute？(1)

2008-04-14 benben000|2008-04-14 InterRonaldo